diff -bpBuN -r -X - linux-sgi-20010406/arch/mips/Makefile linux+1/arch/mips/Makefile --- linux-sgi-20010406/arch/mips/Makefile Tue Apr 3 09:24:30 2001 +++ linux+1/arch/mips/Makefile Fri Apr 6 08:52:46 2001 @@ -63,6 +63,9 @@ endif ifdef CONFIG_CPU_MIPS32 GCCFLAGS += -mcpu=r4600 -mips2 -Wa,--trap endif +ifdef CONFIG_CPU_RC32300 +GCCFLAGS += -mcpu=r4600 -mips2 -Wa,--trap +endif ifdef CONFIG_CPU_R5000 GCCFLAGS += -mcpu=r5000 -mips2 -Wa,--trap endif @@ -203,6 +206,17 @@ ifdef CONFIG_MOMENCO_OCELOT LIBS += arch/mips/gt64120/common/gt64120.o arch/mips/gt64120/momenco_ocelot/momenco_ocelot.o SUBDIRS += arch/mips/gt64120/common arch/mips/gt64120/momenco_ocelot LOADADDR += 0x80100000 +endif + +# +# IDT 79S334 evaluation board. +# +ifdef CONFIG_IDT_79S334 +LIBS += arch/mips/idt-boards/generic/idt.o +LIBS += arch/mips/idt-boards/s334/s334.o +SUBDIRS += arch/mips/idt-boards/generic +SUBDIRS += arch/mips/idt-boards/s334 +LOADADDR += 0x80200000 endif # Binary files linux-sgi-20010406/arch/mips/boot/mkboot and linux+1/arch/mips/boot/mkboot differ Binary files linux-sgi-20010406/arch/mips/boot/zImage and linux+1/arch/mips/boot/zImage differ diff -bpBuN -r -X - linux-sgi-20010406/arch/mips/config.in linux+1/arch/mips/config.in --- linux-sgi-20010406/arch/mips/config.in Tue Apr 3 09:24:30 2001 +++ linux+1/arch/mips/config.in Fri Apr 6 08:56:28 2001 @@ -38,6 +38,7 @@ if [ "$CONFIG_EXPERIMENTAL" = "y" ]; the Model-200/210/312/320/325/350/390 CONFIG_NINO_8MB \ Model-500/510 CONFIG_NINO_16MB" CONFIG_NINO_8MB fi + bool 'Support for IDT 79S334 Evaluation board' CONFIG_IDT_79S334 fi bool 'Support for Mips Magnum 4000' CONFIG_MIPS_MAGNUM_4000 bool 'Support for Momentum Ocelot board' CONFIG_MOMENCO_OCELOT @@ -93,6 +94,12 @@ if [ "$CONFIG_MIPS_EV64120" = "y" ]; the define_bool CONFIG_ISA n define_bool CONFIG_MIPS_GT64120 y fi +if [ "$CONFIG_IDT_79S334" = "y" ]; then + define_bool CONFIG_PCI y + if [ "$CONFIG_VT" = "y" ]; then + define_bool CONFIG_PC_KEYB y + fi +fi if [ "$CONFIG_ALGOR_P4032" = "y" ]; then define_bool CONFIG_PCI y @@ -203,6 +210,7 @@ choice 'CPU type' \ R52xx CONFIG_CPU_NEVADA \ R10000 CONFIG_CPU_R10000 \ SB1 CONFIG_CPU_SB1 \ + RC32300 CONFIG_CPU_RC32300 \ MIPS32 CONFIG_CPU_MIPS32" R4x00 bool 'Override CPU Options' CONFIG_CPU_ADVANCED diff -bpBuN -r -X - linux-sgi-20010406/arch/mips/defconfig-idt334-initrd linux+1/arch/mips/defconfig-idt334-initrd --- linux-sgi-20010406/arch/mips/defconfig-idt334-initrd Wed Dec 31 17:00:00 1969 +++ linux+1/arch/mips/defconfig-idt334-initrd Fri Apr 6 08:52:46 2001 @@ -0,0 +1,468 @@ +# +# Automatically generated by make menuconfig: don't edit +# +CONFIG_MIPS=y + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# Machine selection +# +# CONFIG_ACER_PICA_61 is not set +# CONFIG_ALGOR_P4032 is not set +# CONFIG_BAGET_MIPS is not set +# CONFIG_DECSTATION is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +CONFIG_IDT_79S334=y +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_OLIVETTI_M700 is not set +# CONFIG_PMC_CP7000 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_MCA is not set +# CONFIG_SBUS is not set +CONFIG_PCI=y +# CONFIG_ISA is not set +# CONFIG_EISA is not set +# CONFIG_I8259 is not set + +# +# Loadable module support +# +CONFIG_MODULES=y +# CONFIG_MODVERSIONS is not set +# CONFIG_KMOD is not set + +# +# CPU selection +# +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +CONFIG_CPU_MIPS32=y +CONFIG_CPU_ADVANCED=y +# CONFIG_CPU_HAS_LLSC is not set +# CONFIG_CPU_HAS_WB is not set + +# +# General setup +# +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_MIPS_FPU_EMULATOR=y +CONFIG_KCORE_ELF=y +CONFIG_ELF_KERNEL=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_NET=y +CONFIG_PCI_NAMES=y +# CONFIG_SYSVIPC is not set +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y + +# +# Parallel port support +# +# CONFIG_PARPORT is not set +# CONFIG_PCMCIA is not set + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_XD is not set +# CONFIG_PARIDE is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_BLK_DEV_INITRD=y + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set +# CONFIG_BLK_DEV_MD is not set +# CONFIG_MD_LINEAR is not set +# CONFIG_MD_RAID0 is not set +# CONFIG_MD_RAID1 is not set +# CONFIG_MD_RAID5 is not set +# CONFIG_BLK_DEV_LVM is not set +# CONFIG_LVM_PROC_FS is not set + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_NETLINK=y +CONFIG_RTNETLINK=y +# CONFIG_NETLINK_DEV is not set +CONFIG_NETFILTER=y +CONFIG_NETFILTER_DEBUG=y +# CONFIG_FILTER is not set +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_RTNETLINK=y +CONFIG_NETLINK=y +# CONFIG_IP_MULTIPLE_TABLES is not set +# CONFIG_IP_ROUTE_MULTIPATH is not set +# CONFIG_IP_ROUTE_TOS is not set +CONFIG_IP_ROUTE_VERBOSE=y +# CONFIG_IP_ROUTE_LARGE_TABLES is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +CONFIG_SYN_COOKIES=y + +# +# IP: Netfilter Configuration +# +CONFIG_IP_NF_CONNTRACK=y +CONFIG_IP_NF_FTP=y +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_LIMIT=y +CONFIG_IP_NF_MATCH_MAC=y +CONFIG_IP_NF_MATCH_MARK=y +CONFIG_IP_NF_MATCH_MULTIPORT=y +CONFIG_IP_NF_MATCH_TOS=y +CONFIG_IP_NF_MATCH_STATE=y +# CONFIG_IP_NF_MATCH_UNCLEAN is not set +# CONFIG_IP_NF_MATCH_OWNER is not set +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +# CONFIG_IP_NF_TARGET_MIRROR is not set +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_TARGET_TOS=y +CONFIG_IP_NF_TARGET_MARK=y +CONFIG_IP_NF_TARGET_LOG=y +# CONFIG_IPV6 is not set +# CONFIG_KHTTPD is not set +# CONFIG_ATM is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_LLC is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set +# CONFIG_PHONE_IXJ is not set + +# +# ATA/IDE/MFM/RLL support +# +# CONFIG_IDE is not set +# CONFIG_BLK_DEV_IDE_MODES is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI support +# +# CONFIG_SCSI is not set + +# +# I2O device support +# +# CONFIG_I2O is not set +# CONFIG_I2O_PCI is not set +# CONFIG_I2O_BLOCK is not set +# CONFIG_I2O_LAN is not set +# CONFIG_I2O_SCSI is not set +# CONFIG_I2O_PROC is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set +# CONFIG_NET_SB1000 is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_LANCE is not set +# CONFIG_NET_VENDOR_SMC is not set +# CONFIG_NET_VENDOR_RACAL is not set +# CONFIG_AT1700 is not set +# CONFIG_DEPCA is not set +# CONFIG_HP100 is not set +# CONFIG_NET_ISA is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_APRICOT is not set +# CONFIG_CS89x0 is not set +CONFIG_TULIP=y +# CONFIG_DE4X5 is not set +# CONFIG_DGRS is not set +# CONFIG_DM9102 is not set +CONFIG_EEPRO100=y +# CONFIG_EEPRO100_PM is not set +# CONFIG_LNE390 is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_NE3210 is not set +# CONFIG_ES3210 is not set +# CONFIG_8139TOO is not set +# CONFIG_RTL8129 is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_WINBOND_840 is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_LAN_SAA9730 is not set +# CONFIG_NET_POCKET is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_SK98LIN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PPP=y +# CONFIG_PPP_MULTILINK is not set +CONFIG_PPP_ASYNC=y +# CONFIG_PPP_SYNC_TTY is not set +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_BSDCOMP=y +# CONFIG_PPPOE is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices +# +# CONFIG_TR is not set +# CONFIG_NET_FC is not set +# CONFIG_RCPCI is not set +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Old CD-ROM drivers (not SCSI, not IDE) +# +# CONFIG_CD_NO_IDESCSI is not set + +# +# Character devices +# +# CONFIG_VT is not set +CONFIG_SERIAL=y +CONFIG_SERIAL_CONSOLE=y +# CONFIG_SERIAL_EXTENDED is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_UNIX98_PTYS is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_MOUSE is not set + +# +# Joysticks +# +# CONFIG_JOYSTICK is not set +# CONFIG_QIC02_TAPE is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_INTEL_RNG is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# File systems +# +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_ADFS_FS_RW is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_FAT_FS is not set +# CONFIG_MSDOS_FS is not set +# CONFIG_UMSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +CONFIG_CRAMFS=y +CONFIG_RAMFS=y +# CONFIG_ISO9660_FS is not set +# CONFIG_JOLIET is not set +CONFIG_MINIX_FS=y +# CONFIG_NTFS_FS is not set +# CONFIG_NTFS_RW is not set +# CONFIG_HPFS_FS is not set +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +# CONFIG_DEVFS_MOUNT is not set +# CONFIG_DEVFS_DEBUG is not set +# CONFIG_DEVPTS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX4FS_RW is not set +# CONFIG_ROMFS_FS is not set +CONFIG_EXT2_FS=y +# CONFIG_SYSV_FS is not set +# CONFIG_SYSV_FS_WRITE is not set +# CONFIG_UDF_FS is not set +# CONFIG_UDF_RW is not set +# CONFIG_UFS_FS is not set +# CONFIG_UFS_FS_WRITE is not set + +# +# Network File Systems +# +# CONFIG_CODA_FS is not set +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=y +CONFIG_NFSD_V3=y +CONFIG_SUNRPC=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +# CONFIG_SMB_FS is not set +# CONFIG_NCP_FS is not set +# CONFIG_NCPFS_PACKET_SIGNING is not set +# CONFIG_NCPFS_IOCTL_LOCKING is not set +# CONFIG_NCPFS_STRONG is not set +# CONFIG_NCPFS_NFS_NS is not set +# CONFIG_NCPFS_OS2_NS is not set +# CONFIG_NCPFS_SMALLDOS is not set +# CONFIG_NCPFS_NLS is not set +# CONFIG_NCPFS_EXTRAS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_SMB_NLS is not set +# CONFIG_NLS is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB is not set + +# +# Input core support +# +# CONFIG_INPUT is not set + +# +# Kernel hacking +# +CONFIG_CROSSCOMPILE=y +# CONFIG_MIPS_FPE_MODULE is not set +CONFIG_REMOTE_DEBUG=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_MIPS_UNCACHED is not set diff -bpBuN -r -X - linux-sgi-20010406/arch/mips/defconfig-idt334-nfsroot linux+1/arch/mips/defconfig-idt334-nfsroot --- linux-sgi-20010406/arch/mips/defconfig-idt334-nfsroot Wed Dec 31 17:00:00 1969 +++ linux+1/arch/mips/defconfig-idt334-nfsroot Fri Apr 6 12:55:25 2001 @@ -0,0 +1,491 @@ +# +# Automatically generated by make menuconfig: don't edit +# +CONFIG_MIPS=y +# CONFIG_SMP is not set + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y + +# +# Machine selection +# +# CONFIG_ACER_PICA_61 is not set +# CONFIG_ALGOR_P4032 is not set +# CONFIG_BAGET_MIPS is not set +# CONFIG_DECSTATION is not set +# CONFIG_DDB5074 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_NINO is not set +CONFIG_IDT_79S334=y +# CONFIG_MIPS_MAGNUM_4000 is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_DDB5476 is not set +# CONFIG_OLIVETTI_M700 is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_MCA is not set +# CONFIG_SBUS is not set +CONFIG_PCI=y +# CONFIG_ISA is not set +# CONFIG_EISA is not set +# CONFIG_I8259 is not set + +# +# Loadable module support +# +CONFIG_MODULES=y +# CONFIG_MODVERSIONS is not set +# CONFIG_KMOD is not set + +# +# CPU selection +# +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_CPU_RC32300=y +# CONFIG_CPU_MIPS32 is not set +# CONFIG_CPU_ADVANCED is not set +CONFIG_CPU_HAS_LLSC=y +# CONFIG_CPU_HAS_WB is not set + +# +# General setup +# +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_MIPS_FPU_EMULATOR=y +CONFIG_KCORE_ELF=y +CONFIG_ELF_KERNEL=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_NET=y +CONFIG_PCI_NAMES=y +# CONFIG_HOTPLUG is not set +# CONFIG_PCMCIA is not set +# CONFIG_SYSVIPC is not set +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y + +# +# Memory Technology Devices (MTD) +# +# CONFIG_MTD is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_XD is not set +# CONFIG_PARIDE is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_INITRD is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set +# CONFIG_BLK_DEV_MD is not set +# CONFIG_MD_LINEAR is not set +# CONFIG_MD_RAID0 is not set +# CONFIG_MD_RAID1 is not set +# CONFIG_MD_RAID5 is not set +# CONFIG_BLK_DEV_LVM is not set + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_NETLINK=y +CONFIG_RTNETLINK=y +# CONFIG_NETLINK_DEV is not set +CONFIG_NETFILTER=y +CONFIG_NETFILTER_DEBUG=y +# CONFIG_FILTER is not set +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_RTNETLINK=y +CONFIG_NETLINK=y +# CONFIG_IP_MULTIPLE_TABLES is not set +# CONFIG_IP_ROUTE_MULTIPATH is not set +# CONFIG_IP_ROUTE_TOS is not set +CONFIG_IP_ROUTE_VERBOSE=y +# CONFIG_IP_ROUTE_LARGE_TABLES is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +CONFIG_SYN_COOKIES=y + +# +# IP: Netfilter Configuration +# +CONFIG_IP_NF_CONNTRACK=y +CONFIG_IP_NF_FTP=y +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_LIMIT=y +CONFIG_IP_NF_MATCH_MAC=y +CONFIG_IP_NF_MATCH_MARK=y +CONFIG_IP_NF_MATCH_MULTIPORT=y +CONFIG_IP_NF_MATCH_TOS=y +CONFIG_IP_NF_MATCH_TCPMSS=y +CONFIG_IP_NF_MATCH_STATE=y +# CONFIG_IP_NF_MATCH_UNCLEAN is not set +# CONFIG_IP_NF_MATCH_OWNER is not set +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +# CONFIG_IP_NF_TARGET_MIRROR is not set +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_NAT_FTP=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_TARGET_TOS=y +CONFIG_IP_NF_TARGET_MARK=y +CONFIG_IP_NF_TARGET_LOG=y +CONFIG_IP_NF_TARGET_TCPMSS=y +# CONFIG_IPV6 is not set +# CONFIG_KHTTPD is not set +# CONFIG_ATM is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_LLC is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set +# CONFIG_PHONE_IXJ is not set + +# +# ATA/IDE/MFM/RLL support +# +# CONFIG_IDE is not set +# CONFIG_BLK_DEV_IDE_MODES is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI support +# +# CONFIG_SCSI is not set + +# +# I2O device support +# +# CONFIG_I2O is not set +# CONFIG_I2O_PCI is not set +# CONFIG_I2O_BLOCK is not set +# CONFIG_I2O_LAN is not set +# CONFIG_I2O_SCSI is not set +# CONFIG_I2O_PROC is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set +# CONFIG_NET_SB1000 is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_LANCE is not set +# CONFIG_NET_VENDOR_SMC is not set +# CONFIG_NET_VENDOR_RACAL is not set +# CONFIG_AT1700 is not set +# CONFIG_DEPCA is not set +# CONFIG_HP100 is not set +# CONFIG_NET_ISA is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_APRICOT is not set +# CONFIG_CS89x0 is not set +CONFIG_TULIP=y +# CONFIG_DE4X5 is not set +# CONFIG_DGRS is not set +# CONFIG_DM9102 is not set +CONFIG_EEPRO100=y +# CONFIG_EEPRO100_PM is not set +# CONFIG_LNE390 is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_NE3210 is not set +# CONFIG_ES3210 is not set +# CONFIG_8139TOO is not set +# CONFIG_8139TOO_PIO is not set +# CONFIG_8139TOO_TUNE_TWISTER is not set +# CONFIG_8139TOO_8129 is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_WINBOND_840 is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_LAN_SAA9730 is not set +# CONFIG_NET_POCKET is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_SK98LIN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PPP=y +# CONFIG_PPP_MULTILINK is not set +CONFIG_PPP_ASYNC=y +# CONFIG_PPP_SYNC_TTY is not set +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_BSDCOMP=y +# CONFIG_PPPOE is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices +# +# CONFIG_TR is not set +# CONFIG_NET_FC is not set +# CONFIG_RCPCI is not set +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Old CD-ROM drivers (not SCSI, not IDE) +# +# CONFIG_CD_NO_IDESCSI is not set + +# +# Character devices +# +# CONFIG_VT is not set +CONFIG_SERIAL=y +CONFIG_SERIAL_CONSOLE=y +# CONFIG_SERIAL_EXTENDED is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_UNIX98_PTYS is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_MOUSE is not set + +# +# Joysticks +# +# CONFIG_JOYSTICK is not set +# CONFIG_QIC02_TAPE is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_INTEL_RNG is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# File systems +# +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_REISERFS_CHECK is not set +# CONFIG_ADFS_FS is not set +# CONFIG_ADFS_FS_RW is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_FAT_FS is not set +# CONFIG_MSDOS_FS is not set +# CONFIG_UMSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +CONFIG_CRAMFS=y +CONFIG_RAMFS=y +# CONFIG_ISO9660_FS is not set +# CONFIG_JOLIET is not set +CONFIG_MINIX_FS=y +# CONFIG_NTFS_FS is not set +# CONFIG_NTFS_RW is not set +# CONFIG_HPFS_FS is not set +CONFIG_PROC_FS=y +# CONFIG_DEVFS_FS is not set +# CONFIG_DEVFS_MOUNT is not set +# CONFIG_DEVFS_DEBUG is not set +# CONFIG_DEVPTS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX4FS_RW is not set +# CONFIG_ROMFS_FS is not set +CONFIG_EXT2_FS=y +# CONFIG_SYSV_FS is not set +# CONFIG_SYSV_FS_WRITE is not set +# CONFIG_UDF_FS is not set +# CONFIG_UDF_RW is not set +# CONFIG_UFS_FS is not set +# CONFIG_UFS_FS_WRITE is not set + +# +# Network File Systems +# +# CONFIG_CODA_FS is not set +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=y +CONFIG_NFSD_V3=y +CONFIG_SUNRPC=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +# CONFIG_SMB_FS is not set +# CONFIG_NCP_FS is not set +# CONFIG_NCPFS_PACKET_SIGNING is not set +# CONFIG_NCPFS_IOCTL_LOCKING is not set +# CONFIG_NCPFS_STRONG is not set +# CONFIG_NCPFS_NFS_NS is not set +# CONFIG_NCPFS_OS2_NS is not set +# CONFIG_NCPFS_SMALLDOS is not set +# CONFIG_NCPFS_NLS is not set +# CONFIG_NCPFS_EXTRAS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_SMB_NLS is not set +# CONFIG_NLS is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +# CONFIG_USB is not set + +# +# Input core support +# +# CONFIG_INPUT is not set + +# +# Kernel hacking +# +CONFIG_CROSSCOMPILE=y +# CONFIG_MIPS_FPE_MODULE is not set +CONFIG_REMOTE_DEBUG=y +# CONFIG_LL_DEBUG is not set +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_MIPS_UNCACHED is not set diff -bpBuN -r -X - linux-sgi-20010406/arch/mips/idt-boards/generic/Makefile linux+1/arch/mips/idt-boards/generic/Makefile --- linux-sgi-20010406/arch/mips/idt-boards/generic/Makefile Wed Dec 31 17:00:00 1969 +++ linux+1/arch/mips/idt-boards/generic/Makefile Fri Apr 6 08:52:46 2001 @@ -0,0 +1,22 @@ +# +# Makefile for the idt-boards generic +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). +# + +.S.s: + $(CPP) $(CFLAGS) $< -o $*.s +.S.o: + $(CC) $(CFLAGS) -c $< -o $*.o + +all: idt.o + +O_TARGET := idt.o + +obj-y := irq.o time.o idtIRQ.o serial_gdb.o pci.o idt_mm.o + +obj-$(CONFIG_BLK_DEV_INITRD) += ../../boot/ramdisk.o + +include $(TOPDIR)/Rules.make diff -bpBuN -r -X - linux-sgi-20010406/arch/mips/idt-boards/generic/idtIRQ.S linux+1/arch/mips/idt-boards/generic/idtIRQ.S --- linux-sgi-20010406/arch/mips/idt-boards/generic/idtIRQ.S Wed Dec 31 17:00:00 1969 +++ linux+1/arch/mips/idt-boards/generic/idtIRQ.S Fri Apr 6 08:52:46 2001 @@ -0,0 +1,62 @@ +/* $Id: idtIRQ.S,v 1.4 2000/09/13 14:53:08 jensenq Exp $ + * + * idtIRQ.S - low-level interrupt handler for IDT RC323xx + * + * Copyright (C) 2000,2001 by Lineo, Inc. + * RC323xx support by Quinn Jensen (jensenq@lineo.com) + * Patterned after indyIRQ.S + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * + */ + +#include +#include +#include +#include + +/* + * Everything but timer goes through idt_interrupt() + * + */ + .text + .set noreorder + .set noat + .align 5 + NESTED(idtIRQ, PT_SIZE, sp) + SAVE_ALL + CLI + + .set at + .set noreorder + + mfc0 t0, CP0_CAUSE # get irq mask + nop + mfc0 t1, CP0_STATUS + nop + and s0, t0, t1 # mask cause with status + + /* check for r4k counter/timer IRQ. */ + + andi a0, s0, CAUSEF_IP7 + bne a0, zero, 1f + move a0, sp + + /* something else */ + + move a0, sp + jal idt_interrupt + nop + + j ret_from_irq + nop + +1: + /* timer interrupt */ + + jal mips_timer_interrupt + nop # delay slot + + j ret_from_irq + nop # delay slot + + END(idtIRQ) diff -bpBuN -r -X - linux-sgi-20010406/arch/mips/idt-boards/generic/idt_mm.c linux+1/arch/mips/idt-boards/generic/idt_mm.c --- linux-sgi-20010406/arch/mips/idt-boards/generic/idt_mm.c Wed Dec 31 17:00:00 1969 +++ linux+1/arch/mips/idt-boards/generic/idt_mm.c Fri Apr 6 10:38:52 2001 @@ -0,0 +1,734 @@ +/* + * Quinn Jensen, jensenq@lineo.com + * Copyright (C) 2001 Lineo, Inc. All rights reserved. + * + * IDT 79RC323xx variant of mips32.c, and r4xx0.c + * + * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * MIPS32 CPU variant specific MMU/Cache routines. + */ +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/* CP0 hazard avoidance. */ +#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \ + "nop; nop; nop; nop; nop; nop;\n\t" \ + ".set reorder\n\t") + +/* Primary cache parameters. */ +static int icache_size, dcache_size; /* Size in bytes */ +static int ic_lsize, dc_lsize; /* LineSize in bytes */ + +#include +#include + +#undef DEBUG_CACHE + +/* + * Zero an entire page. + */ + +static void r4k_clear_page_mips32(void * page) +{ + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + ".set\tmips3\n\t" + "addiu\t$1,%0,%2\n" + "1:\tcache\t%3,(%0)\n\t" + "sw\t$0,0(%0)\n\t" + "sw\t$0,4(%0)\n\t" + "sw\t$0,8(%0)\n\t" + "sw\t$0,12(%0)\n\t" + "cache\t%3,16(%0)\n\t" + "sw\t$0,16(%0)\n\t" + "sw\t$0,20(%0)\n\t" + "sw\t$0,24(%0)\n\t" + "sw\t$0,28(%0)\n\t" + "addiu\t%0,64\n\t" + "cache\t%3,-32(%0)\n\t" + "sw\t$0,-32(%0)\n\t" + "sw\t$0,-28(%0)\n\t" + "sw\t$0,-24(%0)\n\t" + "sw\t$0,-20(%0)\n\t" + "cache\t%3,-16(%0)\n\t" + "sw\t$0,-16(%0)\n\t" + "sw\t$0,-12(%0)\n\t" + "sw\t$0,-8(%0)\n\t" + "bne\t$1,%0,1b\n\t" + "sw\t$0,-4(%0)\n\t" + ".set\tmips0\n\t" + ".set\tat\n\t" + ".set\treorder" + :"=r" (page) + :"0" (page), + "I" (PAGE_SIZE), + "i" (Create_Dirty_Excl_D) + :"$1","memory"); +} + +static void r4k_copy_page_mips32(void * to, void * from) +{ + unsigned long dummy1, dummy2; + unsigned long reg1, reg2, reg3, reg4; + + __asm__ __volatile__( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + ".set\tmips3\n\t" + "addiu\t$1,%0,%8\n" + "1:\tcache\t%9,(%0)\n\t" + "lw\t%2,(%1)\n\t" + "lw\t%3,4(%1)\n\t" + "lw\t%4,8(%1)\n\t" + "lw\t%5,12(%1)\n\t" + "sw\t%2,(%0)\n\t" + "sw\t%3,4(%0)\n\t" + "sw\t%4,8(%0)\n\t" + "sw\t%5,12(%0)\n\t" + "cache\t%9,16(%0)\n\t" + "lw\t%2,16(%1)\n\t" + "lw\t%3,20(%1)\n\t" + "lw\t%4,24(%1)\n\t" + "lw\t%5,28(%1)\n\t" + "sw\t%2,16(%0)\n\t" + "sw\t%3,20(%0)\n\t" + "sw\t%4,24(%0)\n\t" + "sw\t%5,28(%0)\n\t" + "cache\t%9,32(%0)\n\t" + "addiu\t%0,64\n\t" + "addiu\t%1,64\n\t" + "lw\t%2,-32(%1)\n\t" + "lw\t%3,-28(%1)\n\t" + "lw\t%4,-24(%1)\n\t" + "lw\t%5,-20(%1)\n\t" + "sw\t%2,-32(%0)\n\t" + "sw\t%3,-28(%0)\n\t" + "sw\t%4,-24(%0)\n\t" + "sw\t%5,-20(%0)\n\t" + "cache\t%9,-16(%0)\n\t" + "lw\t%2,-16(%1)\n\t" + "lw\t%3,-12(%1)\n\t" + "lw\t%4,-8(%1)\n\t" + "lw\t%5,-4(%1)\n\t" + "sw\t%2,-16(%0)\n\t" + "sw\t%3,-12(%0)\n\t" + "sw\t%4,-8(%0)\n\t" + "bne\t$1,%0,1b\n\t" + "sw\t%5,-4(%0)\n\t" + ".set\tmips0\n\t" + ".set\tat\n\t" + ".set\treorder" + :"=r" (dummy1), "=r" (dummy2), + "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4) + :"0" (to), "1" (from), + "I" (PAGE_SIZE), + "i" (Create_Dirty_Excl_D)); +} + +static inline void r4k_flush_cache_all_rc323xx(void) +{ + unsigned long flags; + + /* + * Unfortunately, on the 323xx, just knowing the linesize and + * cache size isn't enough. The dcache is only 2KB, but the + * way is still selected by bit 12, so you either have to + * pretend that it's at least an 8KB cache, or blast the two 1K + * ways separately. We'll do the latter, because the flush + * will take 1/4 the time (but admittedly it's probably infrequent + * enough not to care much). If more MIPS CPU variants do this, all + * of the flush routines could be generalized to handle way size + * and offset in addition to line and cache size. -qj + */ + + save_and_cli(flags); + blast_dcache_rc323xx(); blast_icache16(); + restore_flags(flags); +} + +/* + * On architectures like the Sparc, we could get rid of lines in + * the cache created only by a certain context, but on the MIPS + * (and actually certain Sparc's) we cannot. + */ + +/* If the addresses passed to these routines are valid, they are + * either: + * + * 1) In KSEG0, so we can do a direct flush of the page. + * 2) In KSEG2, and since every process can translate those + * addresses all the time in kernel mode we can do a direct + * flush. + * 3) In KSEG1, no flush necessary. + */ + +static void r4k_flush_page_to_ram_d16i16(struct page * page) +{ + unsigned long addr = (unsigned long)page_address(page) & PAGE_MASK; + + if ((addr >= KSEG0 && addr < KSEG1) || (addr >= KSEG2)) { + unsigned long flags; + +#ifdef DEBUG_CACHE + printk("cram[%08lx]", addr); +#endif + __save_and_cli(flags); + blast_dcache16_page(addr); + __restore_flags(flags); + } +} + +static void r4k_flush_cache_range_rc323xx(struct mm_struct *mm, + unsigned long start, + unsigned long end) +{ + if (mm->context != 0) { +#ifdef DEBUG_CACHE + printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end); +#endif + r4k_flush_cache_all_rc323xx(); + } +} + +static void r4k_flush_cache_mm_rc323xx(struct mm_struct *mm) +{ + if (mm->context != 0) { +#ifdef DEBUG_CACHE + printk("cmm[%d]", (int)mm->context); +#endif + r4k_flush_cache_all_rc323xx(); + } +} + +static void r4k_flush_cache_page_rc323xx(struct vm_area_struct *vma, + unsigned long page) +{ + struct mm_struct *mm = vma->vm_mm; + unsigned long flags; + pgd_t *pgdp; + pmd_t *pmdp; + pte_t *ptep; + int text; + + /* + * If ownes no valid ASID yet, cannot possibly have gotten + * this page into the cache. + */ + if (mm->context == 0) + return; + +#ifdef DEBUG_CACHE + printk("cpage[%d,%08lx]", (int)mm->context, page); +#endif + save_and_cli(flags); + page &= PAGE_MASK; + pgdp = pgd_offset(mm, page); + pmdp = pmd_offset(pgdp, page); + ptep = pte_offset(pmdp, page); + + /* If the page isn't marked valid, the page cannot possibly be + * in the cache. + */ + if (!(pte_val(*ptep) & _PAGE_VALID)) + goto out; + + text = (vma->vm_flags & VM_EXEC); + /* + * Doing flushes for another ASID than the current one is + * too difficult since stupid R4k caches do a TLB translation + * for every cache flush operation. So we do indexed flushes + * in that case, which doesn't overly flush the cache too much. + */ + if (mm == current->active_mm) { + blast_dcache16_page(page); + if(text) + blast_icache16_page(page); + } else { + /* Do indexed flush, too much work to get the (possible) + * tlb refills to work correctly. + */ + page = (KSEG0 + (page & (dcache_size - 1))); + blast_dcache_rc323xx_page_indexed(page); + if(text) + blast_icache_rc323xx_page_indexed(page); + } +out: + restore_flags(flags); +} + +static void +mips32_flush_icache_range(unsigned long start, unsigned long end) +{ + flush_cache_all(); +} + +static void +mips32_flush_icache_page_rc323xx(struct vm_area_struct *vma, struct page *page) +{ + int address; + unsigned long flags; + + if (!(vma->vm_flags & VM_EXEC)) + return; + + address = KSEG0 + ((unsigned long)page_address(page) & PAGE_MASK & (dcache_size - 1)); + __save_and_cli(flags); + blast_icache_rc323xx_page_indexed(address); + __restore_flags(flags); +} + +/* + * Writeback and invalidate the primary cache dcache before DMA. + * + * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D, + * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only + * operate correctly if the internal data cache refill buffer is empty. These + * CACHE instructions should be separated from any potential data cache miss + * by a load instruction to an uncached address to empty the response buffer." + * (Revision 2.0 device errata from IDT available on http://www.idt.com/ + * in .pdf format.) + */ +static void +r4k_dma_cache_wback_inv_pc(unsigned long addr, unsigned long size) +{ + unsigned long end, a; + unsigned int flags; + + if (size >= dcache_size) { + flush_cache_all(); + } else { + /* Workaround for R4600 bug. See comment above. */ + __save_and_cli(flags); + *(volatile unsigned long *)KSEG1; + + a = addr & ~(dc_lsize - 1); + end = (addr + size) & ~(dc_lsize - 1); + while (1) { + flush_dcache_line(a); /* Hit_Writeback_Inv_D */ + if (a == end) break; + a += dc_lsize; + } + __restore_flags(flags); + } + bc_wback_inv(addr, size); +} + +static void +r4k_dma_cache_inv_pc(unsigned long addr, unsigned long size) +{ + unsigned long end, a; + unsigned int flags; + + if (size >= dcache_size) { + flush_cache_all(); + } else { + /* Workaround for R4600 bug. See comment above. */ + __save_and_cli(flags); + *(volatile unsigned long *)KSEG1; + + a = addr & ~(dc_lsize - 1); + end = (addr + size) & ~(dc_lsize - 1); + while (1) { + flush_dcache_line(a); /* Hit_Writeback_Inv_D */ + if (a == end) break; + a += dc_lsize; + } + __restore_flags(flags); + } + + bc_inv(addr, size); +} + +static void +r4k_dma_cache_wback(unsigned long addr, unsigned long size) +{ + panic("r4k_dma_cache called - should not happen.\n"); +} + +/* + * While we're protected against bad userland addresses we don't care + * very much about what happens in that case. Usually a segmentation + * fault will dump the process later on anyway ... + */ +static void r4k_flush_cache_sigtramp(unsigned long addr) +{ + unsigned long daddr, iaddr; + + daddr = addr & ~(dc_lsize - 1); + + __asm__ __volatile__("nop;nop;nop;nop"); /* R4600 V1.7 */ + protected_writeback_dcache_line(daddr); + protected_writeback_dcache_line(daddr + dc_lsize); + iaddr = addr & ~(ic_lsize - 1); + protected_flush_icache_line(iaddr); + protected_flush_icache_line(iaddr + ic_lsize); +} + +#undef DEBUG_TLB +#undef DEBUG_TLBUPDATE + +void flush_tlb_all(void) +{ + unsigned long flags; + unsigned long old_ctx; + int entry; + +#ifdef DEBUG_TLB + printk("[tlball]"); +#endif + + __save_and_cli(flags); + /* Save old context and create impossible VPN2 value */ + old_ctx = (get_entryhi() & 0xff); + set_entrylo0(0); + set_entrylo1(0); + BARRIER; + + entry = get_wired(); + + /* Blast 'em all away. */ + while(entry < mips_cpu.tlbsize) { + /* 4kc will machine-check if multiple hits */ + set_entryhi(KSEG0 + entry * 0x2000); + set_index(entry); + BARRIER; + tlb_write_indexed(); + BARRIER; + entry++; + } + BARRIER; + set_entryhi(old_ctx); + __restore_flags(flags); +} + +void flush_tlb_mm(struct mm_struct *mm) +{ + if (mm->context != 0) { + unsigned long flags; + +#ifdef DEBUG_TLB + printk("[tlbmm<%d>]", mm->context); +#endif + __save_and_cli(flags); + get_new_mmu_context(mm, asid_cache); + if (mm == current->active_mm) + set_entryhi(mm->context & 0xff); + __restore_flags(flags); + } +} + +void flush_tlb_range(struct mm_struct *mm, unsigned long start, + unsigned long end) +{ + if (mm->context != 0) { + unsigned long flags; + int size; + +#ifdef DEBUG_TLB + printk("[tlbrange<%02x,%08lx,%08lx>]", (mm->context & 0xff), + start, end); +#endif + __save_and_cli(flags); + size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; + size = (size + 1) >> 1; + if (size <= mips_cpu.tlbsize/2) { + int oldpid = (get_entryhi() & 0xff); + int newpid = (mm->context & 0xff); + + start &= (PAGE_MASK << 1); + end += ((PAGE_SIZE << 1) - 1); + end &= (PAGE_MASK << 1); + while(start < end) { + int idx; + + set_entryhi(start | newpid); + start += (PAGE_SIZE << 1); + BARRIER; + tlb_probe(); + BARRIER; + idx = get_index(); + set_entrylo0(0); + set_entrylo1(0); + set_entryhi(KSEG0 + 0x2000 * idx); + BARRIER; + if (idx < 0) + continue; + tlb_write_indexed(); + BARRIER; + } + set_entryhi(oldpid); + } else { + get_new_mmu_context(mm, asid_cache); + if (mm == current->active_mm) + set_entryhi(mm->context & 0xff); + } + __restore_flags(flags); + } +} + +void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) +{ + if (vma->vm_mm->context != 0) { + unsigned long flags; + int oldpid, newpid, idx; + +#ifdef DEBUG_TLB + printk("[tlbpage<%d,%08lx>]", vma->vm_mm->context, page); +#endif + newpid = (vma->vm_mm->context & 0xff); + page &= (PAGE_MASK << 1); + __save_and_cli(flags); + oldpid = (get_entryhi() & 0xff); + set_entryhi(page | newpid); + BARRIER; + tlb_probe(); + BARRIER; + idx = get_index(); + set_entrylo0(0); + set_entrylo1(0); + set_entryhi(KSEG0 + 0x2000 * idx); + BARRIER; + if (idx < 0) + goto finish; + tlb_write_indexed(); + + finish: + BARRIER; + set_entryhi(oldpid); + __restore_flags(flags); + } +} + +void pgd_init(unsigned long page) +{ + unsigned long *p = (unsigned long *) page; + int i; + + for(i = 0; i < USER_PTRS_PER_PGD; i+=8) { + p[i + 0] = (unsigned long) invalid_pte_table; + p[i + 1] = (unsigned long) invalid_pte_table; + p[i + 2] = (unsigned long) invalid_pte_table; + p[i + 3] = (unsigned long) invalid_pte_table; + p[i + 4] = (unsigned long) invalid_pte_table; + p[i + 5] = (unsigned long) invalid_pte_table; + p[i + 6] = (unsigned long) invalid_pte_table; + p[i + 7] = (unsigned long) invalid_pte_table; + } +} + +/* + * Updates the TLB with the new pte(s). + */ +void update_mmu_cache(struct vm_area_struct * vma, + unsigned long address, pte_t pte) +{ + unsigned long flags; + pgd_t *pgdp; + pmd_t *pmdp; + pte_t *ptep; + int idx, pid; + + /* + * Handle debugger faulting in for debugee. + */ + if (current->active_mm != vma->vm_mm) + return; + + pid = get_entryhi() & 0xff; + +#ifdef DEBUG_TLB + if ((pid != (vma->vm_mm->context & 0xff)) || (vma->vm_mm->context == 0)) { + printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%d tlbpid=%d\n", + (int) (vma->vm_mm->context & 0xff), pid); + } +#endif + + __save_and_cli(flags); + address &= (PAGE_MASK << 1); + set_entryhi(address | (pid)); + pgdp = pgd_offset(vma->vm_mm, address); + BARRIER; + tlb_probe(); + BARRIER; + pmdp = pmd_offset(pgdp, address); + idx = get_index(); + ptep = pte_offset(pmdp, address); + BARRIER; + set_entrylo0(pte_val(*ptep++) >> 6); + set_entrylo1(pte_val(*ptep) >> 6); + set_entryhi(address | (pid)); + BARRIER; + if (idx < 0) { + tlb_write_random(); + } else { + tlb_write_indexed(); + } + BARRIER; + set_entryhi(pid); + BARRIER; + __restore_flags(flags); +} + +void show_regs(struct pt_regs * regs) +{ + /* Saved main processor registers. */ + printk("$0 : %08lx %08lx %08lx %08lx\n", + 0UL, regs->regs[1], regs->regs[2], regs->regs[3]); + printk("$4 : %08lx %08lx %08lx %08lx\n", + regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]); + printk("$8 : %08lx %08lx %08lx %08lx\n", + regs->regs[8], regs->regs[9], regs->regs[10], regs->regs[11]); + printk("$12: %08lx %08lx %08lx %08lx\n", + regs->regs[12], regs->regs[13], regs->regs[14], regs->regs[15]); + printk("$16: %08lx %08lx %08lx %08lx\n", + regs->regs[16], regs->regs[17], regs->regs[18], regs->regs[19]); + printk("$20: %08lx %08lx %08lx %08lx\n", + regs->regs[20], regs->regs[21], regs->regs[22], regs->regs[23]); + printk("$24: %08lx %08lx\n", + regs->regs[24], regs->regs[25]); + printk("$28: %08lx %08lx %08lx %08lx\n", + regs->regs[28], regs->regs[29], regs->regs[30], regs->regs[31]); + + /* Saved cp0 registers. */ + printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\n", + regs->cp0_epc, regs->cp0_status, regs->cp0_cause); +} + +void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, + unsigned long entryhi, unsigned long pagemask) +{ + unsigned long flags; + unsigned long wired; + unsigned long old_pagemask; + unsigned long old_ctx; + + __save_and_cli(flags); + /* Save old context and create impossible VPN2 value */ + old_ctx = (get_entryhi() & 0xff); + old_pagemask = get_pagemask(); + wired = get_wired(); + set_wired (wired + 1); + set_index (wired); + BARRIER; + set_pagemask (pagemask); + set_entryhi(entryhi); + set_entrylo0(entrylo0); + set_entrylo1(entrylo1); + BARRIER; + tlb_write_indexed(); + BARRIER; + + set_entryhi(old_ctx); + BARRIER; + set_pagemask (old_pagemask); + flush_tlb_all(); + __restore_flags(flags); +} + +/* Detect and size the various caches. */ +static void __init probe_icache(unsigned long config) +{ + icache_size = 1 << ( 9 + ((config >> 9) & 7)); + if ((config >> 5) & 1) panic("Unknown RC323xx Icache configuration detected"); + ic_lsize = 16; + mips_cpu.icache.linesz = ic_lsize; + + printk("Primary instruction cache %dkb, linesize %d bytes (%d ways)\n", + icache_size >> 10, ic_lsize, mips_cpu.icache.ways); +} + +static void __init probe_dcache(unsigned long config) +{ + dcache_size = 1 << ( 9 + ((config >> 6) & 7)); + if ((config >> 4) & 1) panic("Unknown RC323xx Dcache configuration detected"); + dc_lsize = 16; + mips_cpu.dcache.linesz = dc_lsize; + + printk("Primary data cache %dkb, linesize %d bytes (%d ways)\n", + dcache_size >> 10, dc_lsize, mips_cpu.dcache.ways); +} + +static void __init setup_noscache_funcs(void) +{ + _clear_page = (void *)r4k_clear_page_mips32; + _copy_page = (void *)r4k_copy_page_mips32; + _flush_cache_all = r4k_flush_cache_all_rc323xx; + ___flush_cache_all = r4k_flush_cache_all_rc323xx; + _flush_cache_mm = r4k_flush_cache_mm_rc323xx; + _flush_cache_range = r4k_flush_cache_range_rc323xx; + _flush_cache_page = r4k_flush_cache_page_rc323xx; + _flush_page_to_ram = r4k_flush_page_to_ram_d16i16; + + _flush_icache_page = mips32_flush_icache_page_rc323xx; + + _dma_cache_wback_inv = r4k_dma_cache_wback_inv_pc; + _dma_cache_wback = r4k_dma_cache_wback; + _dma_cache_inv = r4k_dma_cache_inv_pc; +} + +static void __init probe_tlb(unsigned long config) +{ + mips_cpu.tlbsize = 16; + + printk("Number of TLB entries %d.\n", mips_cpu.tlbsize); +} + +void __init ld_mmu_rc323xx(void) +{ + unsigned long config = read_32bit_cp0_register(CP0_CONFIG); + + printk("CPU revision is: %08x\n", read_32bit_cp0_register(CP0_PRID)); + + probe_icache(config); + probe_dcache(config); + setup_noscache_funcs(); + probe_tlb(config); + + _flush_cache_sigtramp = r4k_flush_cache_sigtramp; + _flush_icache_range = mips32_flush_icache_range; /* Ouch */ + + flush_cache_all(); +#ifdef CONFIG_MIPS_UNCACHED + change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); +#else + change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT); +#endif + + __flush_cache_all(); + write_32bit_cp0_register(CP0_WIRED, 0); + + /* + * You should never change this register: + * - The entire mm handling assumes the c0_pagemask register to + * be set for 4kb pages. + */ + write_32bit_cp0_register(CP0_PAGEMASK, PM_4K); + flush_tlb_all(); +} diff -bpBuN -r -X - linux-sgi-20010406/arch/mips/idt-boards/generic/irq.c linux+1/arch/mips/idt-boards/generic/irq.c --- linux-sgi-20010406/arch/mips/idt-boards/generic/irq.c Wed Dec 31 17:00:00 1969 +++ linux+1/arch/mips/idt-boards/generic/irq.c Fri Apr 6 09:36:19 2001 @@ -0,0 +1,170 @@ +/* + * IRQ handling for IDT79S334 board + * + * Copyright (C) 2000,2001 by Lineo, Inc. + * Written by Quinn Jensen (jensenq@lineo.com) + * Based on indy_int.c + * + */ + +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_REMOTE_DEBUG +int remote_debug = 0; +#endif + +extern asmlinkage void idtIRQ(void); + +struct irqaction { + void (*handler)(int, void *, struct pt_regs *); + int flags; + int mask; + const char *name; + void *dev_id; + struct irqaction *next; + int count; +} *irq_action = NULL; + +unsigned long spurious_count = 0; + +int (*irq_cannonicalize)(int irq); + +static int idt_irq_cannonicalize(int irq) +{ + return irq; /* Sane hardware, sane code ... */ +} + +extern void set_debug_traps(void); +extern void breakpoint(void); + +void __init init_IRQ(void) +{ +#ifdef CONFIG_REMOTE_DEBUG + if(remote_debug) { + set_debug_traps(); + breakpoint(); + } +#endif + irq_cannonicalize = idt_irq_cannonicalize; + set_except_vector(0, idtIRQ); +} + +irq_cpustat_t irq_stat[1]; +extern char *burst_sr(unsigned int sr); +extern char *burst_cause(unsigned int cause); + +int get_irq_list(char *buf) +{ + int len = 0; + struct irqaction *action; + + len += sprintf(buf + len, "int status: %x\n", *((unsigned char *)0xb0000000)); + + for(action = irq_action; action; action = action->next) { + len += sprintf(buf + len, "%s[%d] ", action->name, action->count); + } + len += sprintf(buf + len, "\n"); + + return len; +} + +unsigned long probe_irq_on(void) /* returns 0 on failure */ +{ + printk("stubbed probe_irq_on()\n"); + return 0; +} + +int probe_irq_off(unsigned long irqs) /* returns 0 or negative on failure */ +{ + printk("stubbed probe_irq_off()\n"); + return -1; +} + +// #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) +#define ALLINTS (IE_IRQ1 | IE_IRQ5) + +extern void idt_disp_char(int, char); + +asmlinkage void idt_interrupt(struct pt_regs *regs) +{ + struct irqaction *action; + unsigned long flags; + + save_and_cli(flags); + + idt_disp_char(2, 'I'); + for(action = irq_action; action; action = action->next) { + action->count++; + action->handler(0, action->dev_id, regs); + } + idt_disp_char(2, 'i'); + + restore_flags(flags); +} + +int request_irq(unsigned int irq, void (*handler)(int, void *, struct pt_regs *), + unsigned long irqflags, const char * devname, void *dev_id) +{ + struct irqaction *action; + + printk("request_irq: irq=%d name=%s dev_id=%x\n", irq, devname, dev_id); + + action = (struct irqaction *)kmalloc(sizeof *action, GFP_KERNEL); + + if(!action) return -ENOMEM; + + action->handler = handler; + action->flags = irqflags; + action->mask = 0; + action->name = devname; + action->count = 0; + action->dev_id = dev_id; + + action->next = irq_action; + irq_action = action; + + set_cp0_status(ALLINTS); + + return 0; +} + +void free_irq(unsigned int irq, void *dev_id) +{ + struct irqaction *action, *prev = NULL; + unsigned long flags; + + printk("free_irq: irq=%d dev_id=%x\n", irq, dev_id); + + for(action = irq_action; action; action = action->next) { + if(action->dev_id == dev_id) { + save_and_cli(flags); + if(prev) { + prev->next = action->next; + } else { + irq_action = action->next; + } + restore_flags(flags); + kfree(action); + return; + } + } + + printk("free_irq: couldn't find handler, sorry\n"); +} + +void enable_irq(unsigned int irq) +{ + printk("stubbed enable_irq(%d)\n", irq); +} + +void disable_irq(unsigned int irq) +{ + printk("stubbed disable_irq(%d)\n", irq); +} diff -bpBuN -r -X - linux-sgi-20010406/arch/mips/idt-boards/generic/pci.c linux+1/arch/mips/idt-boards/generic/pci.c --- linux-sgi-20010406/arch/mips/idt-boards/generic/pci.c Wed Dec 31 17:00:00 1969 +++ linux+1/arch/mips/idt-boards/generic/pci.c Fri Apr 6 08:52:46 2001 @@ -0,0 +1,368 @@ +/* + * pci.c - PCI support for IDT 79S33X boards using + * the RC32300 family CPU core with integrated PCI bridge + * + * Copyright (C) 2000,2001 by Lineo, Inc. + * Quinn Jensen (jensenq@lineo.com) + * Based on arch/mips/ddb5074/pci.c -- NEC DDB Vrc-5074 PCI access routines + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * + */ + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_PCI + +#define PCI_CFG_CTRL ((volatile unsigned long *)0xb8002cf8) +#define PCI_CFG_DATA ((volatile unsigned long *)0xb8002cfc) +#define PCI_REG_BASE 0xb8000000 + +static __inline__ int pci_range_ck(unsigned char bus, unsigned char dev) +{ + if (bus == 0 && dev <= 4) + return 0; /* OK device number */ + + return -1; /* NOT ok device number */ +} + +#define PCI_CFG_SET(dev,fun,off) \ + ((*PCI_CFG_CTRL) = (0x80000000 | ((dev)<<11) | \ + ((fun)<<8) | (off))) + +static int idt_pcibios_read_config_dword (struct pci_dev *pdev, int offset, unsigned int *val) +{ + unsigned char bus = pdev->bus->number; + unsigned char dev = pdev->devfn; + unsigned char fun = dev & 0x07; + + dev >>= 3; + if (offset & 0x3) { + return PCIBIOS_BAD_REGISTER_NUMBER; + } + if (pci_range_ck(bus, dev)) { + *val = 0xFFFFFFFF; + return PCIBIOS_DEVICE_NOT_FOUND; + } + PCI_CFG_SET(dev, fun, offset); + *val = *PCI_CFG_DATA; + + return PCIBIOS_SUCCESSFUL; +} + +static int idt_pcibios_read_config_word (struct pci_dev *pdev, int offset, unsigned short *val) +{ + unsigned char bus = pdev->bus->number; + unsigned char dev = pdev->devfn; + unsigned char fun = dev & 0x07; + + dev >>= 3; + if (offset & 0x1) { + return PCIBIOS_BAD_REGISTER_NUMBER; + } + if (pci_range_ck(bus, dev)) { + *val = 0xffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + PCI_CFG_SET(dev, fun, (offset & ~0x3)); + *val = *PCI_CFG_DATA >> ((offset & 3) * 8); + + return PCIBIOS_SUCCESSFUL; +} + +static int idt_pcibios_read_config_byte (struct pci_dev *pdev, int offset, unsigned char *val) +{ + unsigned char bus = pdev->bus->number; + unsigned char dev = pdev->devfn; + unsigned char fun = dev & 0x07; + + dev >>= 3; + if (pci_range_ck(bus, dev)) { + *val = 0xff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + PCI_CFG_SET(dev, fun, (offset & ~0x3)); + *val = *PCI_CFG_DATA >> ((offset & 3) * 8); + + return PCIBIOS_SUCCESSFUL; +} + +static int idt_pcibios_write_config_dword (struct pci_dev *pdev, int offset, unsigned int val) +{ + unsigned char bus = pdev->bus->number; + unsigned char dev = pdev->devfn; + unsigned char fun = dev & 0x07; + + dev >>= 3; + if(offset & 0x3) { + return PCIBIOS_BAD_REGISTER_NUMBER; + } + if (pci_range_ck(bus, dev)) { + return PCIBIOS_DEVICE_NOT_FOUND; + } + PCI_CFG_SET(dev, fun, offset); + *PCI_CFG_DATA = val; + return PCIBIOS_SUCCESSFUL; +} + +static int idt_pcibios_write_config_word (struct pci_dev *pdev, int offset, unsigned short val) +{ + unsigned char bus = pdev->bus->number; + unsigned char dev = pdev->devfn; + unsigned char fun = dev & 0x07; + unsigned long tmp; + + dev >>= 3; + if (offset & 0x1) { + return PCIBIOS_BAD_REGISTER_NUMBER; + } + if (pci_range_ck(bus, dev)) { + return PCIBIOS_DEVICE_NOT_FOUND; + } + PCI_CFG_SET(dev, fun, (offset & ~0x3)); + tmp = *PCI_CFG_DATA; + tmp &= ~(0xffff << ((offset & 0x3) * 8)); + tmp |= (val << ((offset & 0x3) * 8)); + *PCI_CFG_DATA = tmp; + return PCIBIOS_SUCCESSFUL; +} + +static int idt_pcibios_write_config_byte (struct pci_dev *pdev, int offset, unsigned char val) +{ + unsigned char bus = pdev->bus->number; + unsigned char dev = pdev->devfn; + unsigned char fun = dev & 0x07; + unsigned long tmp; + + dev >>= 3; + if (pci_range_ck(bus, dev)) { + return PCIBIOS_DEVICE_NOT_FOUND; + } + PCI_CFG_SET(dev, fun, (offset & ~0x3)); + tmp = *PCI_CFG_DATA; + tmp &= ~(0xff << ((offset & 0x3) * 8)); + tmp |= (val << ((offset & 0x3) * 8)); + *PCI_CFG_DATA = tmp; + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops idt_pci_ops = { + idt_pcibios_read_config_byte, + idt_pcibios_read_config_word, + idt_pcibios_read_config_dword, + idt_pcibios_write_config_byte, + idt_pcibios_write_config_word, + idt_pcibios_write_config_dword +}; + +static void dump_pci_config(char *note, struct pci_dev *dev) +{ + unsigned char pin, line, burst, latency; + unsigned short vendor, device, command, status; + int slot_num; + + slot_num = PCI_SLOT(dev->devfn); + + idt_pcibios_read_config_word(dev, PCI_VENDOR_ID, &vendor); + idt_pcibios_read_config_word(dev, PCI_DEVICE_ID, &device); + idt_pcibios_read_config_word(dev, PCI_COMMAND, &command); + idt_pcibios_read_config_word(dev, PCI_STATUS, &status); + idt_pcibios_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &burst); + idt_pcibios_read_config_byte(dev, PCI_LATENCY_TIMER, &latency); + idt_pcibios_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); + idt_pcibios_read_config_byte(dev, PCI_INTERRUPT_LINE, &line); + + printk("PCI slot %d: dev=%04x:%04x cmd=%04x stat=%04x lsize=%d late=%d int pin=%d line=%d %s\n", + slot_num, dev->vendor, dev->device, command, status, burst, latency, pin, line, note); +} + +static void __init pcibios_fixup_irqs(void) +{ + struct pci_dev *dev; + + printk("pcibios_fixup_irqs:\n"); + + pci_for_each_dev(dev) { + int slot_num = PCI_SLOT(dev->devfn); + + dump_pci_config("", dev); + + switch (slot_num) { + default: + idt_pcibios_write_config_word(dev, PCI_COMMAND, 0x007); + idt_pcibios_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0); + idt_pcibios_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40); + break; + } + + dump_pci_config("(new settings)", dev); + } +} + +void __init pcibios_init(void) +{ + printk("PCI: Initializing PCI\n"); + + /* allow writes to bridge config space */ + + *(volatile unsigned long *)(PCI_REG_BASE + 0x20e0) = 4; + + /* why did IDT use 0x032410b5 here? The book says it's vendor 111d device 0204 */ + *PCI_CFG_CTRL = 0x80000000; *PCI_CFG_DATA = 0x032410b5; /* device, vendor */ + *PCI_CFG_CTRL = 0x80000004; *PCI_CFG_DATA = 0x02a00157; /* status, command */ + *PCI_CFG_CTRL = 0x80000008; *PCI_CFG_DATA = 0x06800001; /* class code, revision id */ + *PCI_CFG_CTRL = 0x8000000C; *PCI_CFG_DATA = 0x0000ff01; /* BIST, header type, latency, cache line size */ + *PCI_CFG_CTRL = 0x80000010; *PCI_CFG_DATA = 0x00000000; /* PCI memory base address (as target) */ + *PCI_CFG_CTRL = 0x80000014; *PCI_CFG_DATA = 0x00000000; /* reserved */ + *PCI_CFG_CTRL = 0x80000018; *PCI_CFG_DATA = 0x10000001; /* I/O base address */ + *PCI_CFG_CTRL = 0x8000001C; *PCI_CFG_DATA = 0x00000000; /* reserved */ + *PCI_CFG_CTRL = 0x80000020; *PCI_CFG_DATA = 0x00000000; /* reserved */ + *PCI_CFG_CTRL = 0x80000024; *PCI_CFG_DATA = 0x00000000; /* reserved */ + *PCI_CFG_CTRL = 0x80000028; *PCI_CFG_DATA = 0x00000000; /* reserved */ + *PCI_CFG_CTRL = 0x8000002C; *PCI_CFG_DATA = 0x013410b5; /* subsystem id, vendor */ + *PCI_CFG_CTRL = 0x80000030; *PCI_CFG_DATA = 0x00000000; /* reserved */ + *PCI_CFG_CTRL = 0x80000034; *PCI_CFG_DATA = 0x00000000; /* reserved */ + *PCI_CFG_CTRL = 0x80000038; *PCI_CFG_DATA = 0x00000000; /* reserved */ + *PCI_CFG_CTRL = 0x8000003C; *PCI_CFG_DATA = 0x38080101; /* max lat, min gnt, interrupt pin, line */ + *PCI_CFG_CTRL = 0x80000040; *PCI_CFG_DATA = 0x00008080; /* retry timeout, trdy timeout */ + +#ifdef __MIPSEB__ +#define ENDIANNESS_BIT 1 +#else +#define ENDIANNESS_BIT 0 +#endif + + /* + * CPU -> PCI accesses + * + * CPU physical address 40000000 is PCI memory space 1. 32 MB of + * virtual address starting at E0000000 are pointed there by a + * wired TLB entry. The space is marked uncached. + * + * Where this range maps to in PCI memory space is specified by the + * top 4 bits of the 20b0 regigster. + */ + + *(volatile unsigned long *)(PCI_REG_BASE + 0x20b0) = 0x40000000 | ENDIANNESS_BIT; /* mem space 1 */ + *(volatile unsigned long *)(PCI_REG_BASE + 0x20b8) = 0x50000000 | ENDIANNESS_BIT; /* mem space 2 */ + *(volatile unsigned long *)(PCI_REG_BASE + 0x20c0) = 0x0 | ENDIANNESS_BIT; /* mem space 3 */ + *(volatile unsigned long *)(PCI_REG_BASE + 0x20c8) = 0x0 | ENDIANNESS_BIT; /* i/o space */ + + *(volatile unsigned long *)(PCI_REG_BASE + 0x20e0) = 0; /* round robin arbitration */ + + /* + * PCI -> CPU accesses + * + * Let PCI see system memory at the bottom where it really is. + */ + + *(volatile unsigned long *)(PCI_REG_BASE + 0x20e8) = 0x0 | ENDIANNESS_BIT; /* mem space */ + *(volatile unsigned long *)(PCI_REG_BASE + 0x2100) = 0x0 | ENDIANNESS_BIT; /* i/o space */ + + + *PCI_CFG_CTRL = 0x00000000; + + printk("PCI: Probing PCI hardware\n"); + + iomem_resource.start = 0x40000000; + iomem_resource.end = 0x41ffffff; + + pci_scan_bus(0, &idt_pci_ops, NULL); + pci_assign_unassigned_resources(); + pcibios_fixup_irqs(); +} + +void __init pcibios_fixup_bus(struct pci_bus *bus) +{ +} + +char *pcibios_setup (char *str) +{ + return str; +} + +void __init pcibios_update_irq(struct pci_dev *dev, int irq) +{ + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); +} + +void __init pcibios_fixup_pbus_ranges(struct pci_bus *bus, + struct pbus_set_ranges_data *ranges) +{ + ranges->io_start -= bus->resource[0]->start; + ranges->io_end -= bus->resource[0]->start; + ranges->mem_start -= bus->resource[1]->start; + ranges->mem_end -= bus->resource[1]->start; +} + +int pcibios_enable_resources(struct pci_dev *dev) +{ + u16 cmd, old_cmd; + int idx; + struct resource *r; + + pci_read_config_word(dev, PCI_COMMAND, &cmd); + old_cmd = cmd; + for(idx=0; idx<6; idx++) { + r = &dev->resource[idx]; + if (!r->start && r->end) { + printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", dev->slot_name); + return -EINVAL; + } + if (r->flags & IORESOURCE_IO) + cmd |= PCI_COMMAND_IO; + if (r->flags & IORESOURCE_MEM) + cmd |= PCI_COMMAND_MEMORY; + } + if (cmd != old_cmd) { + printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd); + pci_write_config_word(dev, PCI_COMMAND, cmd); + } + return 0; +} + +int pcibios_enable_device(struct pci_dev *dev) +{ + return pcibios_enable_resources(dev); +} + +void pcibios_update_resource(struct pci_dev *dev, struct resource *root, + struct resource *res, int resource) +{ + u32 new, check; + int reg; + + new = res->start | (res->flags & PCI_REGION_FLAG_MASK); + if (resource < 6) { + reg = PCI_BASE_ADDRESS_0 + 4*resource; + } else if (resource == PCI_ROM_RESOURCE) { + res->flags |= PCI_ROM_ADDRESS_ENABLE; + reg = dev->rom_base_reg; + } else { + /* Somebody might have asked allocation of a non-standard resource */ + return; + } + + pci_write_config_dword(dev, reg, new); + pci_read_config_dword(dev, reg, &check); + if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) { + printk(KERN_ERR "PCI: Error while updating region " + "%s/%d (%08x != %08x)\n", dev->slot_name, resource, + new, check); + } +} + +void pcibios_align_resource(void *data, struct resource *res, + unsigned long size) +{ + struct pci_dev *dev = data; +} + +struct pci_fixup pcibios_fixups[] = {}; + +#endif /* CONFIG_PCI */ + diff -bpBuN -r -X - linux-sgi-20010406/arch/mips/idt-boards/generic/serial_gdb.c linux+1/arch/mips/idt-boards/generic/serial_gdb.c --- linux-sgi-20010406/arch/mips/idt-boards/generic/serial_gdb.c Wed Dec 31 17:00:00 1969 +++ linux+1/arch/mips/idt-boards/generic/serial_gdb.c Fri Apr 6 08:52:46 2001 @@ -0,0 +1,206 @@ +/* + * serial_gdb.c - polling driver for 16550 UART in IDT RC323xx + * + * Copyright (C) 2000,2001 by Lineo, Inc. + * Written by Quinn Jensen (jensenq@lineo.com) + * + */ +#include + +/* set remote gdb baud rate at 115200 */ + +#define GDB_BAUD 115200 + +extern unsigned int idt_cpu_freq; + +#define DIVISOR (idt_cpu_freq * 1000 * 1000 / 16 / GDB_BAUD) + +/* turn this on to watch the debug protocol echoed on the console port */ +#undef DEBUG_REMOTE_DEBUG + +#ifdef __MIPSEB__ +#define CONS_PORT 0xb8000803 +#define GDB_PORT 0xb8000823 +#else +#define CONS_PORT 0xb8000800 +#define GDB_PORT 0xb8000820 +#endif + +volatile unsigned char *ports[2] = { + (volatile unsigned char *)CONS_PORT, + (volatile unsigned char *)GDB_PORT +}; + + +void reset_gdb_port(void); +void cons_putc(char c); +int port_getc(int port); +void port_putc(int port, char c); + +int cons_getc(void) +{ + return port_getc(0); +} + +void cons_putc(char c) +{ + port_putc(0, c); +} + +void cons_puts(char *s) +{ + while(*s) { + if(*s == '\n') cons_putc('\r'); + cons_putc(*s); + s++; + } +} + +void cons_do_putn(int n) +{ + if(n) { + cons_do_putn(n / 10); + cons_putc(n % 10 + '0'); + } +} + +void cons_putn(int n) +{ + if(n < 0) { + cons_putc('-'); + n = -n; + } + + if (n == 0) { + cons_putc('0'); + } else { + cons_do_putn(n); + } +} + +#ifdef DEBUG_REMOTE_DEBUG +static enum {HUH, SENDING, GETTING} state; + +static void sent(int c) +{ + switch(state) { + case HUH: + case GETTING: + cons_puts("\nSNT "); + state = SENDING; + /* fall through */ + case SENDING: + cons_putc(c); + break; + } +} + +static void got(int c) +{ + switch(state) { + case HUH: + case SENDING: + cons_puts("\nGOT "); + state = GETTING; + /* fall through */ + case GETTING: + cons_putc(c); + break; + } +} +#endif /* DEBUG_REMOTE */ + +static int first = 1; + +int getDebugChar(void) +{ + int c; + + if(first) reset_gdb_port(); + + c = port_getc(1); + +#ifdef DEBUG_REMOTE_DEBUG + got(c); +#endif + + return c; +} + +int port_getc(int p) +{ + volatile unsigned char *port = ports[p]; + int c; + + while((*(port + UART_LSR * 4) & UART_LSR_DR) == 0) { + continue; + } + + c = *(port + UART_RX * 4); + + return c; +} + +void putDebugChar(char c) +{ + if(first) reset_gdb_port(); + +#ifdef DEBUG_REMOTE_DEBUG + sent(c); +#endif + idt_disp_char(3, '%'); + port_putc(1, c); +} + +#define OK_TO_XMT (UART_LSR_TEMT | UART_LSR_THRE) + +void port_putc(int p, char c) +{ + volatile unsigned char *port = ports[p]; + volatile unsigned char *lsr = port + UART_LSR * 4; + + while((*lsr & OK_TO_XMT) != OK_TO_XMT) { + continue; + } + + *(port + UART_TX * 4) = c; +} + +void reset_gdb_port(void) +{ + volatile unsigned char *port = ports[1]; + + first = 0; + + cons_puts("reset_gdb_port: initializing remote debug serial port (internal UART 1, "); + cons_putn(GDB_BAUD); + cons_puts("baud, MHz="); + cons_putn(idt_cpu_freq); + cons_puts(", divisor="); + cons_putn(DIVISOR); + cons_puts(")\n"); + + /* reset the port */ + *(port + UART_CSR * 4) = 0; + + /* clear and enable the FIFOs */ + *(port + UART_FCR * 4) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | + UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14; + + /* set the baud rate */ + *(port + UART_LCR * 4) = UART_LCR_DLAB; /* enable DLL, DLM registers */ + *(port + UART_DLL * 4) = DIVISOR; + *(port + UART_DLM * 4) = DIVISOR >> 8; + + /* set the line control stuff and disable DLL, DLM regs */ + + *(port + UART_LCR * 4) = UART_LCR_STOP | /* 2 stop bits */ + UART_LCR_WLEN8; /* 8 bit word length */ + + /* leave interrupts off */ + *(port + UART_IER * 4) = 0; + + /* the modem controls don't leave the chip on this port, so leave them alone */ + *(port + UART_MCR * 4) = 0; + +} diff -bpBuN -r -X - linux-sgi-20010406/arch/mips/idt-boards/generic/time.c linux+1/arch/mips/idt-boards/generic/time.c --- linux-sgi-20010406/arch/mips/idt-boards/generic/time.c Wed Dec 31 17:00:00 1969 +++ linux+1/arch/mips/idt-boards/generic/time.c Fri Apr 6 11:36:29 2001 @@ -0,0 +1,256 @@ +/* + * time.c for IDT 79S33X boards + * based on time.c but modified to work around having no RTC + * Quinn Jensen, jensenq@lineo.com + * Copyright (C) 2001 Lineo, Inc. + * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * Setting up the clock on the MIPS boards. + * + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +extern volatile unsigned long wall_jiffies; +static long last_rtc_update = 0; +unsigned long missed_heart_beats = 0; + +static unsigned long r4k_offset; /* Amount to increment compare reg each time */ +static unsigned long r4k_cur; /* What counter should be at next timer irq */ +extern rwlock_t xtime_lock; + +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) + +static unsigned int timer_tick_count=0; + + +static inline void ack_r4ktimer(unsigned long newval) +{ + write_32bit_cp0_register(CP0_COMPARE, newval); +} + + +static int set_rtc_mmss(unsigned long nowtime) +{ + return 0; +} + +/* + * There are a lot of conceptually broken versions of the MIPS timer interrupt + * handler floating around. This one is rather different, but the algorithm + * is provably more robust. + */ +void mips_timer_interrupt(struct pt_regs *regs) +{ + int irq = 7; + + if (r4k_offset == 0) + goto null; + + do { + kstat.irqs[0][irq]++; + do_timer(regs); + + if ((timer_tick_count++ % HZ) == 0) { + extern void idt_disp_char(int, char); + static int toggle = 0; + toggle ^= 1; + idt_disp_char(0, toggle ? 'U' : 'u'); + } + + r4k_cur += r4k_offset; + ack_r4ktimer(r4k_cur); + + } while (((unsigned long)read_32bit_cp0_register(CP0_COUNT) + - r4k_cur) < 0x7fffffff); + + return; + +null: + ack_r4ktimer(0); +} + +/* + * Figure out the r4k offset, the amount to increment the compare + * register for each time tick. + * Use the RTC to calculate offset. + */ +static unsigned long __init cal_r4koff(void) +{ + unsigned long count; + extern unsigned int idt_cpu_freq; + + count = idt_cpu_freq * 1000 * 1000; + + return (count / HZ); +} + +static unsigned long __init get_mips_time(void) +{ + return mktime(2001, 4, 6, 0, 0, 0); +} + +void __init time_init(void) +{ + unsigned int est_freq, flags; + + printk("calculating r4koff... "); + r4k_offset = cal_r4koff(); + printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset); + + est_freq = 2*r4k_offset*HZ; + est_freq += 5000; /* round */ + est_freq -= est_freq%10000; + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, + (est_freq%1000000)*100/1000000); + r4k_cur = (read_32bit_cp0_register(CP0_COUNT) + r4k_offset); + + write_32bit_cp0_register(CP0_COMPARE, r4k_cur); + set_cp0_status(ALLINTS); + + /* Read time from the RTC chipset. */ + write_lock_irqsave (&xtime_lock, flags); + xtime.tv_sec = get_mips_time(); + xtime.tv_usec = 0; + write_unlock_irqrestore(&xtime_lock, flags); +} + +/* This is for machines which generate the exact clock. */ +#define USECS_PER_JIFFY (1000000/HZ) +#define USECS_PER_JIFFY_FRAC (0x100000000*1000000/HZ&0xffffffff) + +/* Cycle counter value at the previous timer interrupt.. */ + +static unsigned int timerhi = 0, timerlo = 0; + +/* + * FIXME: Does playing with the RP bit in c0_status interfere with this code? + */ +static unsigned long do_fast_gettimeoffset(void) +{ + u32 count; + unsigned long res, tmp; + + /* Last jiffy when do_fast_gettimeoffset() was called. */ + static unsigned long last_jiffies=0; + unsigned long quotient; + + /* + * Cached "1/(clocks per usec)*2^32" value. + * It has to be recalculated once each jiffy. + */ + static unsigned long cached_quotient=0; + + tmp = jiffies; + + quotient = cached_quotient; + + if (tmp && last_jiffies != tmp) { + last_jiffies = tmp; + if (last_jiffies != 0) { + unsigned long r0; + do_div64_32(r0, timerhi, timerlo, tmp); + do_div64_32(quotient, USECS_PER_JIFFY, + USECS_PER_JIFFY_FRAC, r0); + cached_quotient = quotient; + } + } + + /* Get last timer tick in absolute kernel time */ + count = read_32bit_cp0_register(CP0_COUNT); + + /* .. relative to previous jiffy (32 bits is enough) */ + count -= timerlo; + + __asm__("multu\t%1,%2\n\t" + "mfhi\t%0" + :"=r" (res) + :"r" (count), + "r" (quotient)); + + /* + * Due to possible jiffies inconsistencies, we need to check + * the result so that we'll get a timer that is monotonic. + */ + if (res >= USECS_PER_JIFFY) + res = USECS_PER_JIFFY-1; + + return res; +} + +void do_gettimeofday(struct timeval *tv) +{ + unsigned int flags; + + read_lock_irqsave (&xtime_lock, flags); + *tv = xtime; + tv->tv_usec += do_fast_gettimeoffset(); + + /* + * xtime is atomically updated in timer_bh. jiffies - wall_jiffies + * is nonzero if the timer bottom half hasnt executed yet. + */ + if (jiffies - wall_jiffies) + tv->tv_usec += USECS_PER_JIFFY; + + read_unlock_irqrestore (&xtime_lock, flags); + + if (tv->tv_usec >= 1000000) { + tv->tv_usec -= 1000000; + tv->tv_sec++; + } +} + +void do_settimeofday(struct timeval *tv) +{ + write_lock_irq (&xtime_lock); + + /* This is revolting. We need to set the xtime.tv_usec correctly. + * However, the value in this location is is value at the last tick. + * Discover what correction gettimeofday would have done, and then + * undo it! + */ + tv->tv_usec -= do_fast_gettimeoffset(); + + if (tv->tv_usec < 0) { + tv->tv_usec += 1000000; + tv->tv_sec--; + } + + xtime = *tv; + time_adjust = 0; /* stop active adjtime() */ + time_status |= STA_UNSYNC; + time_maxerror = NTP_PHASE_LIMIT; + time_esterror = NTP_PHASE_LIMIT; + + write_unlock_irq (&xtime_lock); +} diff -bpBuN -r -X - linux-sgi-20010406/arch/mips/idt-boards/s334/Makefile linux+1/arch/mips/idt-boards/s334/Makefile --- linux-sgi-20010406/arch/mips/idt-boards/s334/Makefile Wed Dec 31 17:00:00 1969 +++ linux+1/arch/mips/idt-boards/s334/Makefile Fri Apr 6 08:52:46 2001 @@ -0,0 +1,20 @@ +# +# Makefile for the IDT 79S334 board specific stuff +# +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). +# + +.S.s: + $(CPP) $(CFLAGS) $< -o $*.s +.S.o: + $(CC) $(CFLAGS) -c $< -o $*.o + +all: s334.o + +O_TARGET := s334.o + +obj-y := prom.o setup.o + +include $(TOPDIR)/Rules.make diff -bpBuN -r -X - linux-sgi-20010406/arch/mips/idt-boards/s334/prom.c linux+1/arch/mips/idt-boards/s334/prom.c --- linux-sgi-20010406/arch/mips/idt-boards/s334/prom.c Wed Dec 31 17:00:00 1969 +++ linux+1/arch/mips/idt-boards/s334/prom.c Fri Apr 6 08:52:46 2001 @@ -0,0 +1,248 @@ +/* + * prom.c - PROM console driver for IDT79S334 board + * + * Copyright (C) 2000,2001 by Lineo, Inc. + * Written by Quinn Jensen (jensenq@lineo.com) + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PROM_ENTRY(x) (0xbfc00000+((x)*8)) +#define NVRAM_ENVSIZE ((volatile unsigned char *)0xb2000004) +#define NVRAM_ENVSTART ((volatile unsigned char *)0xb2000040) + +extern void cons_putc(char c); +extern void cons_puts(char *s); + +void (*prom_puts)(char *str) = cons_puts; +void (*prom_putchar)(char c) = cons_putc; +int (*prom_getchar)(void) = (int (*)(void))PROM_ENTRY(11); + +char arcs_cmdline[COMMAND_LINE_SIZE]; +unsigned int idt_cpu_freq = 75; /* default to 75 MHz */ + +#ifdef CONFIG_REMOTE_DEBUG +extern int remote_debug; +#endif + +/* + * register serial ports at run time when we can compute baud_base + */ + +#ifdef __MIPSEB__ +#define IDT_BASE 0xb8000803 +#else +#define IDT_BASE 0xb8000800 +#endif + +struct serial_struct idt_serial[2] = { + {flags: STD_COM_FLAGS, iomem_base: (u8 *)(IDT_BASE), + iomem_reg_shift: 2, io_type: SERIAL_IO_MEM}, + {flags: STD_COM_FLAGS, iomem_base: (u8 *)(IDT_BASE + 0x20), + iomem_reg_shift: 2, io_type: SERIAL_IO_MEM}, +}; + +void prom_setup_cmdline(void) +{ + char *cmdp = arcs_cmdline; + int clen = COMMAND_LINE_SIZE - 1; + char *envp = (char *)NVRAM_ENVSTART; + + /* stored size is 2 bytes, big endian order */ + + int esize = (*NVRAM_ENVSIZE << 8) + *(NVRAM_ENVSIZE + 1); + + if(esize < 0 || esize > 512) return; /* bad format */ + + *cmdp = '\0'; + + /* copy relevant env vars from the nvram + * + * prom environment variables of the form "bootparm?=stuff" + * are combined in the order they appear in the nvram to + * to form the boot command line. e.g. + * + * bootaddr=1.2.3.4 + * bootparm1=root=/dev/nfs + * bootparm2=nfsroot=/home/nfsroot,nolock + * + * becomes + * + * root=/dev/nfs nfsroot=/home/nfsroot,nolock + */ + + for(;;) { + unsigned int elen = *envp & 0xFF; /* first byte is length */ + char tmp_env[256], *env = tmp_env; + + if(elen == 0 || elen > esize) break; /* bad format */ + + strncpy(env, envp, elen); + env[elen] = '\0'; + + /* bump to next prom variable */ + + envp += elen; + esize -= elen; + + /* skip over the length byte */ + + env++; + elen--; + + /* check for one of ours */ + + if(strncmp(env, "bootparm", 8) == 0) { + unsigned int vlen; + + /* skip beyond the '=' and trim to fit */ + + env += 10; + vlen = elen - 10; + if(clen < vlen + 2) vlen = clen; + + /* copy it */ + + memcpy(cmdp, env, vlen); + cmdp += vlen; clen -= vlen; + + /* add a blank and null terminate */ + + *cmdp++ = ' '; clen--; + *cmdp = '\0'; + } else if(strncmp(env, "MHZ=", 4) == 0) { + idt_cpu_freq = simple_strtoul(env + 4, 0, 10); + printk("CPU Clock at %d MHz (from MHZ environment variable)\n", idt_cpu_freq); + } + + /* all done? */ + + if(clen <= 0) break; + if(esize <= 0) break; + } + + if(arcs_cmdline[0]) printk("command line: %s\n", arcs_cmdline); + +} + +void prom_console_write(struct console *con, const char *s, unsigned count) +{ + int i; + + for(i = 0; i < count; i++, s++) { + if(*s == '\n') prom_putchar('\r'); + prom_putchar(*s); + } +} + +kdev_t prom_console_device(struct console *con) +{ + return MKDEV(TTY_MAJOR, 64 + con->index); +} + +int prom_console_wait_key(struct console *con) +{ + return prom_getchar(); +} + +int prom_console_setup(struct console *con, char *options) +{ + return 0; +} + +struct console prom_console_driver = { + "ttyS", + prom_console_write, /* write */ + NULL, /* read */ + prom_console_device, /* device */ + prom_console_wait_key, /* wait_key */ + NULL, /* unblank */ + prom_console_setup, /* setup */ + CON_PRINTBUFFER, + -1, + 0, + NULL +}; + +extern unsigned long mips_machgroup; +extern unsigned long mips_machtype; + +#define PFN_UP(x) (((x) + PAGE_SIZE-1) >> PAGE_SHIFT) +#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK) + +/* IDT 79S334 memory map -- we really should be auto sizing it */ + +#define RAM_SIZE (32*1024*1024) +#define RAM_FIRST 0x80000400 /* leave room for exception vectors */ +#define RAM_END (0x80000000 + RAM_SIZE) + +extern void _ftext, _end; + +int __init prom_init(int argc, char **argv, char **envp) +{ + /* turn on the console */ +#ifdef CONFIG_LL_DEBUG + register_console(&prom_console_driver); +#endif + /* set up command line */ + + prom_setup_cmdline(); + + /* set console baud rate divisor based on clock freq */ + + idt_serial[0].baud_base = idt_cpu_freq * 1000 * 1000 / 16; + register_serial(&idt_serial[0]); + +#ifndef CONFIG_REMOTE_DEBUG + /* register second port when gdb isn't using it */ + + idt_serial[1].baud_base = idt_cpu_freq * 1000 * 1000 / 16; + register_serial(&idt_serial[1]); +#endif + + /* set our arch type */ + + mips_machgroup = MACH_GROUP_IDT; + mips_machtype = MACH_IDT79S334; + + /* + * give all RAM to boot allocator, + * except where the kernel was loaded + */ + + add_memory_region(RAM_FIRST, + PHYSADDR((unsigned long)&_ftext) - RAM_FIRST, BOOT_MEM_RAM); + add_memory_region(PHYSADDR((unsigned long)&_end), + RAM_SIZE - PHYSADDR((unsigned long)&_end), BOOT_MEM_RAM); + + /* reset the tulip */ + +#if 1 + *(unsigned long *)0xb88fff00 = 1; + udelay(100); + *(unsigned long *)0xb88fff00 = 0x00A00000 | 0x4800; +#endif + +#ifdef CONFIG_REMOTE_DEBUG + if(strstr(arcs_cmdline, "kgdb=on")) { + remote_debug = 1; + } +#endif + + return 0; +} + +void prom_free_prom_memory(void) +{ +} + diff -bpBuN -r -X - linux-sgi-20010406/arch/mips/idt-boards/s334/setup.c linux+1/arch/mips/idt-boards/s334/setup.c --- linux-sgi-20010406/arch/mips/idt-boards/s334/setup.c Wed Dec 31 17:00:00 1969 +++ linux+1/arch/mips/idt-boards/s334/setup.c Fri Apr 6 09:07:13 2001 @@ -0,0 +1,100 @@ +/* + * setup.c - boot time setup code for IDT 79S334 board + * + * Copyright (C) 2000,2001 by Lineo, Inc. + * Written by Quinn Jensen (jensenq@lineo.com) + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include /* for rtc_ops, we fake the RTC */ +#include + +#define DIG_CLEAR ((volatile unsigned char *)0xB4000400) +#define DIG0 ((volatile unsigned char *)0xB400000F) +#define DIG1 ((volatile unsigned char *)0xB4000008) +#define DIG2 ((volatile unsigned char *)0xB4000007) +#define DIG3 ((volatile unsigned char *)0xB4000003) + +void idt_disp_char(int i, char c) +{ + switch(i) { + case 0: *DIG0 = c; break; + case 1: *DIG1 = c; break; + case 2: *DIG2 = c; break; + case 3: *DIG3 = c; break; + default: *DIG0 = '?'; break; + } +} + +void idt_disp_str(char *s) +{ + if(s == 0) { + char c = *DIG_CLEAR; + } else { + int i; + for(i = 0; i < 4; i++) { + if(s[i]) idt_disp_char(i, s[i]); + } + } +} + +static void idt_machine_restart(char *command) +{ + printk("idt_machine_restart: command=%s\n", command); + + /* just jump to the reset vector */ + + ((void (*)(void))0xBFC00000)(); +} + +static void idt_machine_halt(void) +{ + printk("idt_machine_halt: halted\n"); + for(;;) continue; +} + +static void idt_machine_power_off(void) +{ + printk("idt_machine_power_off: It is now safe to turn off the power\n"); + for(;;) continue; +} + +void __init idt_setup(void) +{ + extern void *__rd_start, *__rd_end; + idt_disp_str("Unix"); + + mips_io_port_base = 0xB8800000; + + /* map 0xe0000000 virtual to 0x40000000 phys for PCI */ + write_32bit_cp0_register(CP0_WIRED, 0); /* clear any previous stuff */ + add_wired_entry(0x01000017, 0x01040017, 0xe0000000, PM_16M); +// uncomment for 64 meg of PCI mapping instead of just 32 +// add_wired_entry(0x01080017, 0x010c0017, 0xe2000000, PM_16M); + dump_tlb_all(); + + _machine_restart = idt_machine_restart; + _machine_halt = idt_machine_halt; + _machine_power_off = idt_machine_power_off; + +#ifdef CONFIG_BLK_DEV_INITRD + initrd_start = (unsigned long)&__rd_start; + initrd_end = (unsigned long)&__rd_end; + initrd_below_start_ok = 1; + printk("idt_setup: initrd_start=%x end=%x\n", initrd_start, initrd_end); +#endif + +} + +int page_is_ram(unsigned long pagenr) +{ + return 1; +} diff -bpBuN -r -X - linux-sgi-20010406/arch/mips/kernel/Makefile linux+1/arch/mips/kernel/Makefile --- linux-sgi-20010406/arch/mips/kernel/Makefile Tue Apr 3 09:24:35 2001 +++ linux+1/arch/mips/kernel/Makefile Fri Apr 6 08:57:55 2001 @@ -26,6 +26,9 @@ obj-$(CONFIG_MODULES) += mips_ksyms.o ifdef CONFIG_CPU_R3000 obj-y += r2300_misc.o r2300_fpu.o r2300_switch.o else +ifdef CONFIG_CPU_RC32300 +obj-y += r4k_misc.o r2300_fpu.o r2300_switch.o +else obj-y += r4k_misc.o r4k_switch.o ifdef CONFIG_CPU_R6000 obj-y += r6000_fpu.o @@ -33,6 +36,7 @@ else obj-y += r4k_fpu.o endif endif +endif obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_MIPS_FPE_MODULE) += fpe.o @@ -52,7 +56,9 @@ ifndef CONFIG_DECSTATION ifndef CONFIG_MIPS_ITE8172 ifndef CONFIG_NINO ifndef CONFIG_MIPS_IVR + ifndef CONFIG_IDT_79S334 obj-y += time.o + endif endif endif endif diff -bpBuN -r -X - linux-sgi-20010406/arch/mips/kernel/proc.c linux+1/arch/mips/kernel/proc.c --- linux-sgi-20010406/arch/mips/kernel/proc.c Tue Apr 3 09:24:36 2001 +++ linux+1/arch/mips/kernel/proc.c Fri Apr 6 09:00:11 2001 @@ -41,12 +41,13 @@ int get_cpuinfo(char *buffer) const char *mach_momenco_names[] = GROUP_MOMENCO_NAMES; const char *mach_ite_names[] = GROUP_ITE_NAMES; const char *mach_philips_names[] = GROUP_PHILIPS_NAMES; + const char *mach_idt_names[] = GROUP_IDT_NAMES; const char **mach_group_to_name[] = { mach_unknown_names, mach_jazz_names, mach_dec_names, mach_arc_names, mach_sni_rm_names, mach_acn_names, mach_sgi_names, mach_cobalt_names, mach_nec_ddb_names, mach_baget_names, mach_cosine_names, mach_galileo_names, mach_momenco_names, - mach_ite_names, mach_philips_names}; + mach_ite_names, mach_philips_names, mach_idt_names}; unsigned int version = read_32bit_cp0_register(CP0_PRID); int len; diff -bpBuN -r -X - linux-sgi-20010406/arch/mips/kernel/setup.c linux+1/arch/mips/kernel/setup.c --- linux-sgi-20010406/arch/mips/kernel/setup.c Tue Apr 3 09:24:36 2001 +++ linux+1/arch/mips/kernel/setup.c Fri Apr 6 11:33:49 2001 @@ -299,6 +299,18 @@ static inline void cpu_probe(void) MIPS_CPU_COUNTER | MIPS_CPU_WATCH; mips_cpu.tlbsize = 64; break; +#ifdef CONFIG_CPU_RC32300 + case PRID_IMP_RC32334: + mips_cpu.cputype = CPU_RC32300; + mips_cpu.isa_level = MIPS_CPU_ISA_M32; + mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX | + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | + MIPS_CPU_DIVEC | MIPS_CPU_WATCH; + mips_cpu.tlbsize = 16; + mips_cpu.icache.ways = 2; + mips_cpu.dcache.ways = 2; + break; +#endif default: mips_cpu.cputype = CPU_UNKNOWN; break; @@ -503,6 +515,7 @@ void __init setup_arch(char **cmdline_p) void malta_setup(void); void momenco_ocelot_setup(void); void nino_setup(void); + void idt_setup(void); #ifdef CONFIG_NINO extern void * __rd_start, * __rd_end; @@ -603,6 +616,11 @@ void __init setup_arch(char **cmdline_p) nino_setup(); break; #endif +#ifdef CONFIG_IDT_79S334 + case MACH_GROUP_IDT: + idt_setup(); + break; +#endif default: panic("Unsupported architecture"); } @@ -728,6 +746,7 @@ void __init setup_arch(char **cmdline_p) data_resource.start = virt_to_bus(&_fdata); data_resource.end = virt_to_bus(&_edata) - 1; +#ifndef CONFIG_IDT_79S334 /* * Request address space for all standard RAM. */ @@ -757,6 +776,7 @@ void __init setup_arch(char **cmdline_p) request_resource(res, &code_resource); request_resource(res, &data_resource); } +#endif } void r3081_wait(void) diff -bpBuN -r -X - linux-sgi-20010406/arch/mips/lib/dump_tlb.c linux+1/arch/mips/lib/dump_tlb.c --- linux-sgi-20010406/arch/mips/lib/dump_tlb.c Fri Oct 8 18:00:58 1999 +++ linux+1/arch/mips/lib/dump_tlb.c Fri Apr 6 08:52:46 2001 @@ -15,7 +15,11 @@ #include #include +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_RC32300) +#define mips_tlb_entries 16 +#else #define mips_tlb_entries 48 +#endif void dump_tlb(int first, int last) @@ -43,7 +47,7 @@ dump_tlb(int first, int last) entrylo1 = read_32bit_cp0_register(CP0_ENTRYLO1); /* Unused entries have a virtual address of KSEG0. */ - if ((entryhi & 0xffffe000) != 0x80000000 + if ((entryhi & 0xff000000) != 0x80000000 && (entryhi & 0xff) == asid) { /* * Only print entries in use @@ -54,15 +58,15 @@ dump_tlb(int first, int last) c1 = (entrylo1 >> 3) & 7; printk("va=%08lx asid=%08lx" - " [pa=%06lx c=%d d=%d v=%d g=%ld]" - " [pa=%06lx c=%d d=%d v=%d g=%ld]", + " [pa=%08lx c=%d d=%d v=%d g=%ld]" + " [pa=%08lx c=%d d=%d v=%d g=%ld]\n", (entryhi & 0xffffe000), entryhi & 0xff, - entrylo0 & PAGE_MASK, c0, + entrylo0 << 6 & PAGE_MASK, c0, (entrylo0 & 4) ? 1 : 0, (entrylo0 & 2) ? 1 : 0, (entrylo0 & 1), - entrylo1 & PAGE_MASK, c1, + entrylo1 << 6 & PAGE_MASK, c1, (entrylo1 & 4) ? 1 : 0, (entrylo1 & 2) ? 1 : 0, (entrylo1 & 1)); diff -bpBuN -r -X - linux-sgi-20010406/arch/mips/mm/loadmmu.c linux+1/arch/mips/mm/loadmmu.c --- linux-sgi-20010406/arch/mips/mm/loadmmu.c Tue Apr 3 09:24:40 2001 +++ linux+1/arch/mips/mm/loadmmu.c Fri Apr 6 08:52:46 2001 @@ -47,6 +47,7 @@ extern void ld_mmu_tfp(void); extern void ld_mmu_andes(void); extern void ld_mmu_sb1(void); extern void ld_mmu_mips32(void); +extern void ld_mmu_rc323xx(void); void __init loadmmu(void) { @@ -69,6 +70,10 @@ void __init loadmmu(void) #if defined(CONFIG_CPU_MIPS32) printk("Loading MIPS32 MMU routines.\n"); ld_mmu_mips32(); +#endif +#if defined(CONFIG_CPU_RC32300) + printk("Loading RC323xx MMU routines.\n"); + ld_mmu_rc323xx(); #endif } else switch(mips_cpu.cputype) { #ifdef CONFIG_CPU_R3000 diff -bpBuN -r -X - linux-sgi-20010406/drivers/pci/Makefile linux+1/drivers/pci/Makefile --- linux-sgi-20010406/drivers/pci/Makefile Sun Feb 4 18:33:01 2001 +++ linux+1/drivers/pci/Makefile Fri Apr 6 08:52:46 2001 @@ -23,6 +23,7 @@ obj-$(CONFIG_ALPHA) += setup-bus.o setup obj-$(CONFIG_ARM) += setup-bus.o setup-irq.o obj-$(CONFIG_DDB5476) += setup-bus.o obj-$(CONFIG_SGI_IP27) += setup-irq.o +obj-$(CONFIG_IDT_79S334) += setup-bus.o setup-irq.o ifndef CONFIG_X86 obj-y += syscall.o Binary files linux-sgi-20010406/drivers/pci/gen-devlist and linux+1/drivers/pci/gen-devlist differ diff -bpBuN -r -X - linux-sgi-20010406/include/asm-mips/bootinfo.h linux+1/include/asm-mips/bootinfo.h --- linux-sgi-20010406/include/asm-mips/bootinfo.h Tue Apr 3 09:26:29 2001 +++ linux+1/include/asm-mips/bootinfo.h Fri Apr 6 09:16:09 2001 @@ -30,10 +30,11 @@ #define MACH_GROUP_GLOBESPAN 15 /* Globespan PVR Referrence Board */ #define MACH_GROUP_SIBYTE 16 /* Sibyte Eval Boards */ #define MACH_GROUP_TOSHIBA 17 /* Toshiba Reference Systems TSBREF */ +#define MACH_GROUP_IDT 18 /* IDT Eval Boards */ #define GROUP_NAMES { "unknown", "Jazz", "Digital", "ARC", "SNI", "ACN", \ "SGI", "Cobalt", "NEC DDB", "Baget", "Cosine", "Galileo", "Momentum", \ - "ITE", "Philips", "Globepspan", "SiByte", "Toshiba" } + "ITE", "Philips", "Globepspan", "SiByte", "Toshiba", "IDT" } /* * Valid machtype values for group unknown (low order halfword of mips_machtype) @@ -186,6 +187,13 @@ #define GROUP_TOSHIBA_NAMES { "Pallas", "TopasCE", "JMR" } /* + * Valid machtype for group IDT + */ +#define MACH_IDT79S334 0 + +#define GROUP_IDT_NAMES { "79S334" } + +/* * Valid cputype values */ #define CPU_UNKNOWN 0 @@ -225,14 +233,16 @@ #define CPU_TX3912 34 #define CPU_TX3922 35 #define CPU_TX3927 36 -#define CPU_LAST 36 +#define CPU_RC32300 37 +#define CPU_LAST 37 #define CPU_NAMES { "unknown", "R2000", "R3000", "R3000A", "R3041", "R3051", \ "R3052", "R3081", "R3081E", "R4000PC", "R4000SC", "R4000MC", \ "R4200", "R4400PC", "R4400SC", "R4400MC", "R4600", "R6000", \ "R6000A", "R8000", "R10000", "R4300", "R4650", "R4700", "R5000", \ "R5000A", "R4640", "Nevada", "RM7000", "R5432", "MIPS 4Kc", \ - "MIPS 5Kc", "R4310", "SiByte SB1", "TX3912", "TX3922", "TX3927" } + "MIPS 5Kc", "R4310", "SiByte SB1", "TX3912", "TX3922", "TX3927", \ + "RC32300" } #define COMMAND_LINE_SIZE 256 diff -bpBuN -r -X - linux-sgi-20010406/include/asm-mips/cpu.h linux+1/include/asm-mips/cpu.h --- linux-sgi-20010406/include/asm-mips/cpu.h Tue Apr 3 09:26:29 2001 +++ linux+1/include/asm-mips/cpu.h Fri Apr 6 09:16:11 2001 @@ -44,6 +44,7 @@ #define PRID_IMP_R4300 0x0b00 #define PRID_IMP_R12000 0x0e00 #define PRID_IMP_R8000 0x1000 +#define PRID_IMP_RC32334 0x1800 #define PRID_IMP_R4600 0x2000 #define PRID_IMP_R4700 0x2100 #define PRID_IMP_TX39 0x2200 diff -bpBuN -r -X - linux-sgi-20010406/include/asm-mips/idt-boards/idt323xx_cache.h linux+1/include/asm-mips/idt-boards/idt323xx_cache.h --- linux-sgi-20010406/include/asm-mips/idt-boards/idt323xx_cache.h Wed Dec 31 17:00:00 1969 +++ linux+1/include/asm-mips/idt-boards/idt323xx_cache.h Fri Apr 6 08:52:46 2001 @@ -0,0 +1,257 @@ +/* + * idt323xx_cache.h + * + * Quinn Jensen, jensenq@lineo.com + * Copyright (C) 2001 Lineo, Inc. All rights reserved. + * + * based on mips32_cache.h and r4kcache.h + * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * Inline assembly cache operations. + * + * This file is the original r4cache.c file with modification that makes the + * cache handling more generic. + * + * FIXME: Handle split L2 caches. + * + */ +#ifndef _MIPS_IDT_CACHE_H +#define _MIPS_IDT_CACHE_H + +#include +#include + +extern inline void flush_icache_line_indexed(unsigned long addr) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + ".set mips3\n\t" + "cache %1, (%0)\n\t" + "cache %1, 0x1000(%0)\n\t" // hit the other way, too + ".set mips0\n\t" + ".set reorder" + : + : "r" (addr), + "i" (Index_Invalidate_I)); +} + +extern inline void flush_dcache_line_indexed(unsigned long addr) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + ".set mips3\n\t" + "cache %1, (%0)\n\t" + "cache %1, 0x1000(%0)\n\t" // hit the other way, too + ".set mips0\n\t" + ".set reorder" + : + : "r" (addr), + "i" (Index_Writeback_Inv_D)); +} + +extern inline void flush_icache_line(unsigned long addr) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + ".set mips3\n\t" + "cache %1, (%0)\n\t" + ".set mips0\n\t" + ".set reorder" + : + : "r" (addr), + "i" (Hit_Invalidate_I)); +} + +extern inline void flush_dcache_line(unsigned long addr) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + ".set mips3\n\t" + "cache %1, (%0)\n\t" + ".set mips0\n\t" + ".set reorder" + : + : "r" (addr), + "i" (Hit_Writeback_Inv_D)); +} + +extern inline void invalidate_dcache_line(unsigned long addr) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + ".set mips3\n\t" + "cache %1, (%0)\n\t" + ".set mips0\n\t" + ".set reorder" + : + : "r" (addr), + "i" (Hit_Invalidate_D)); +} + +/* + * The next two are for badland addresses like signal trampolines. + */ +extern inline void protected_flush_icache_line(unsigned long addr) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + ".set mips3\n" + "1:\tcache %1,(%0)\n" + "2:\t.set mips0\n\t" + ".set reorder\n\t" + ".section\t__ex_table,\"a\"\n\t" + STR(PTR)"\t1b,2b\n\t" + ".previous" + : + : "r" (addr), + "i" (Hit_Invalidate_I)); +} + +extern inline void protected_writeback_dcache_line(unsigned long addr) +{ + __asm__ __volatile__( + ".set noreorder\n\t" + ".set mips3\n" + "1:\tcache %1,(%0)\n" + "2:\t.set mips0\n\t" + ".set reorder\n\t" + ".section\t__ex_table,\"a\"\n\t" + STR(PTR)"\t1b,2b\n\t" + ".previous" + : + : "r" (addr), + "i" (Hit_Writeback_D)); +} + +#define cache_unroll(base,op) \ + __asm__ __volatile__(" \ + .set noreorder; \ + .set mips3; \ + cache %1, (%0); \ + .set mips0; \ + .set reorder" \ + : \ + : "r" (base), \ + "i" (op)); + +#define cache16_unroll32(base,op) \ + __asm__ __volatile__(" \ + .set noreorder; \ + .set mips3; \ + cache %1, 0x000(%0); cache %1, 0x010(%0); \ + cache %1, 0x020(%0); cache %1, 0x030(%0); \ + cache %1, 0x040(%0); cache %1, 0x050(%0); \ + cache %1, 0x060(%0); cache %1, 0x070(%0); \ + cache %1, 0x080(%0); cache %1, 0x090(%0); \ + cache %1, 0x0a0(%0); cache %1, 0x0b0(%0); \ + cache %1, 0x0c0(%0); cache %1, 0x0d0(%0); \ + cache %1, 0x0e0(%0); cache %1, 0x0f0(%0); \ + cache %1, 0x100(%0); cache %1, 0x110(%0); \ + cache %1, 0x120(%0); cache %1, 0x130(%0); \ + cache %1, 0x140(%0); cache %1, 0x150(%0); \ + cache %1, 0x160(%0); cache %1, 0x170(%0); \ + cache %1, 0x180(%0); cache %1, 0x190(%0); \ + cache %1, 0x1a0(%0); cache %1, 0x1b0(%0); \ + cache %1, 0x1c0(%0); cache %1, 0x1d0(%0); \ + cache %1, 0x1e0(%0); cache %1, 0x1f0(%0); \ + .set mips0; \ + .set reorder" \ + : \ + : "r" (base), \ + "i" (op)); + +extern inline void blast_dcache16_page(unsigned long page) +{ + unsigned long start = page; + unsigned long end = (start + PAGE_SIZE); + + while(start < end) { + cache16_unroll32(start,Hit_Writeback_Inv_D); + start += 0x200; + } +} + +extern inline void blast_dcache_rc323xx(void) +{ + unsigned long start = KSEG0; + unsigned long end = (start + 1024); + + /* + * The IDT RC323xx dcache indexing is tricky. + * Bit 12 selects the way, while bits 4-9 select the set. + * So do both 1KB ways separately. -qj + */ + while(start < end) { + /* do first way */ + cache16_unroll32(start,Index_Writeback_Inv_D); + /* do second way */ + cache16_unroll32(start | 0x1000,Index_Writeback_Inv_D); + start += 0x200; + } +} + +extern inline void blast_dcache_rc323xx_page_indexed(unsigned long page) +{ + /* + * Since the dcache can't hold a full page, and since + * it's pretty likely we just touched it all, just + * blast the whole cache. -qj + */ + blast_dcache_rc323xx(); +} + +extern inline void blast_icache16(void) +{ + unsigned long start = KSEG0; + unsigned long end = (start + icache_size); + + /* + * Both ways get flushed on the icache ok because + * they're contiguous + */ + while(start < end) { + cache16_unroll32(start,Index_Invalidate_I); + start += 0x200; + } +} + +extern inline void blast_icache16_page(unsigned long page) +{ + unsigned long start = page; + unsigned long end = (start + PAGE_SIZE); + + while(start < end) { + cache16_unroll32(start,Hit_Invalidate_I); + start += 0x200; + } +} + +extern inline void blast_icache_rc323xx_page_indexed(unsigned long page) +{ + /* + * We have to blast the whole 8K because the page + * could have entries in either way. + */ + blast_icache16(); +} + +#endif /* !(_MIPS_IDT_CACHE_H) */ diff -bpBuN -r -X - linux-sgi-20010406/include/asm-mips/io.h linux+1/include/asm-mips/io.h --- linux-sgi-20010406/include/asm-mips/io.h Fri Feb 9 17:43:15 2001 +++ linux+1/include/asm-mips/io.h Fri Apr 6 09:15:17 2001 @@ -149,7 +149,12 @@ extern unsigned long isa_slot_offset; */ extern inline void * ioremap(unsigned long offset, unsigned long size) { +#ifdef CONFIG_IDT_79S334 + /* on the 334 we map the PCI bus to KSEG3 (uncached) */ + return (void *) KSEG3ADDR(offset); +#else return (void *) KSEG1ADDR(offset); +#endif } /* @@ -159,7 +164,12 @@ extern inline void * ioremap(unsigned lo */ extern inline void * ioremap_nocache (unsigned long offset, unsigned long size) { +#ifdef CONFIG_IDT_79S334 + /* on the 334 we map the PCI bus to KSEG3 (uncached) */ + return (void *) KSEG3ADDR(offset); +#else return (void *) KSEG1ADDR(offset); +#endif } extern inline void iounmap(void *addr) diff -bpBuN -r -X - linux-sgi-20010406/include/asm-mips/pci.h linux+1/include/asm-mips/pci.h --- linux-sgi-20010406/include/asm-mips/pci.h Fri Apr 6 08:45:21 2001 +++ linux+1/include/asm-mips/pci.h Fri Apr 6 09:16:55 2001 @@ -1,4 +1,4 @@ -/* $Id: pci.h,v 1.10 2000/03/23 02:26:00 ralf Exp $ +/* $Id: pci.h,v 1.3 2001/01/06 05:10:17 jensenq Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -46,6 +46,13 @@ extern inline void pcibios_penalize_isa_ #undef PCIBIOS_MIN_MEM #define PCIBIOS_MIN_IO 0x0100000 #define PCIBIOS_MIN_MEM 0x1000000 +#endif + +#ifdef CONFIG_IDT_79S334 +#undef PCIBIOS_MIN_IO +#undef PCIBIOS_MIN_MEM +#define PCIBIOS_MIN_IO 0x00000000 +#define PCIBIOS_MIN_MEM 0x00100000 #endif struct pci_dev; diff -bpBuN -r -X - linux-sgi-20010406/include/asm-mips/semaphore-helper.h linux+1/include/asm-mips/semaphore-helper.h --- linux-sgi-20010406/include/asm-mips/semaphore-helper.h Mon Mar 12 15:26:35 2001 +++ linux+1/include/asm-mips/semaphore-helper.h Fri Apr 6 10:39:33 2001 @@ -20,7 +20,7 @@ static inline void wake_one_more(struct atomic_inc(&sem->waking); } -#if !defined(CONFIG_CPU_HAS_LLSC) || defined(CONFIG_CPU_MIPS32) +#if !defined(CONFIG_CPU_HAS_LLSC) || defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_RC32300) /* * It doesn't make sense, IMHO, to endlessly turn interrupts off and on again. diff -bpBuN -r -X - linux-sgi-20010406/include/asm-mips/semaphore.h linux+1/include/asm-mips/semaphore.h --- linux-sgi-20010406/include/asm-mips/semaphore.h Mon Mar 12 15:26:35 2001 +++ linux+1/include/asm-mips/semaphore.h Fri Apr 6 09:16:14 2001 @@ -105,7 +105,7 @@ static inline int down_interruptible(str return ret; } -#if !defined(CONFIG_CPU_HAS_LLSC) || defined(CONFIG_CPU_MIPS32) +#if !defined(CONFIG_CPU_HAS_LLSC) || defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_RC32300) static inline int down_trylock(struct semaphore * sem) {